Hexo

inline

2026-04-28T13:16:41.646Z

内联,重要性不必多说。

基本思路不是很难，

module层面构建call graph
根据call graph根据SCC（强连通分量
遍历SCC尝试内联（注意递归函数）在同一个SCC里面就是一个递归链
决定内联时候：
1. clone被内联函数，用valuemap[old] = new记录映射情况。
2. 被clone内容加入caller中
3. 更新下ssa的def use chain。

主要是各种cost和gain的评估，各种启发式。

inline asm

2026-04-28T13:16:41.646Z

asm volatile (
    "asm template"
    : output_operands        // ← 第一个冒号后
    : input_operands         // ← 第二个冒号后
    : clobbers               // ← 第三个冒号后
);

example:

#include 

__attribute__((noinline))
int mul_add(
    int a, int b, int c,
    int *sum,
    int *acc)
{
    asm volatile (
        "imull  %[b], %[a]\n\t"
        "leal   (%[a], %[c]), %[s]\n\t"
        "addl   %[a], %[acc]\n\t"
        : [a]   "+r"(a),        // read-write
          [s]   "=r"(*sum),     // write-only
          [acc] "+r"(*acc)      // read-write
        : [b]   "r"(b),
          [c]   "r"(c)
        : "cc", "memory"
    );

    return a;
}

%[b] 是命名参数, 与后面的[a]对应。

"+r" read-write
"=r" write only, 新定义一次，不读旧值
"r" read only，只读

使用zola设置github.io作为个人博客

2026-04-28T13:16:41.644Z

步骤如下：

本地安装zola
运行zola init , like zola init myblog

目录如下：

myblog/
├── config.toml          # 配置文件
├── content/             # 内容文件（Markdown）
├── sass/                # Sass 样式文件（可选）
├── static/              # 静态资源（图片、CSS、JS 等）
├── templates/           # 模板文件（HTML）
└── themes/              # 主题文件（可选）

创建的博客就放在content下面。
图片放在static/images下面，在博客里用![test](/images/.png)引用
博客格式：+++一定要有

---
title = "我的第一篇文章"
---

## hello zola

cd && git init将这些目录加到版本控制进去。
添加自定义模板teplates/index.html和teplates/page.html
创建github actions: .github/workflows/deploy.yml
内容如下：

name: Deploy Zola site to GitHub Pages

on:
  push:
    branches:
      - master  # 触发部署的分支

jobs:
  deploy:
    runs-on: ubuntu-latest
    steps:
      - name: Checkout
        uses: actions/checkout@v3

      - name: Install Zola
        run: |
          wget https://github.com/getzola/zola/releases/download/v0.19.2/zola-v0.19.2-x86_64-unknown-linux-gnu.tar.gz
          tar -xzf zola-v0.19.2-x86_64-unknown-linux-gnu.tar.gz
          sudo mv zola /usr/local/bin

      - name: Build site
        run: zola build

      - name: Deploy to GitHub Pages
        uses: shalzz/zola-deploy-action@master
        env:
            PAGES_BRANCH: gh-pages
            TOKEN: ${{ secrets.GITHUB_TOKEN }}

这里注意分支。

master分支是我们源文件的分支
gh-pages分支是制品分支

参考：zola github-actions

推送到 git@github.com:/.github.io.git
设置github pages:
如果上传图片，设置config.toml中base_url = "https://.github.io/"
等待github actions完成，就OK了

部署静态网址到服务器

需要

一个云服务器，带ip地址/域名的

步骤如下

在云服务器安装zola（pre-build比较好）
在服务器安装nginx
拉取博客代码到服务器：git clone example_blog@git
运行命令cd example_blog && zola build -u "". 构建好的文件在example_blog/public下
cp public /var/www/static-site -r
给nginx权限并确保自己有权限sudo chown -R $USER:$USER /var/www/static-site && sudo chown -R www-data:www-data /var/www/static-site && sudo chmod -R 755 /var/www/static-site
修改nginx的配置文件（ai生成的）
- 新建配置文件/etc/nginx/sites-available/static-site.conf
- 添加内容

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
server {
  listen 80;
  server_name example.com;  # 替换为你的域名或服务器 IP（如 192.168.1.100）

  root /var/www/static-site;  # 静态文件根目录
  index index.html index.htm;  # 默认索引文件

  location / {
      try_files $uri $uri/ =404;  # 按顺序查找文件或目录，否则返回 404
  }

  # 可选：启用 Gzip 压缩
  gzip on;
  gzip_types text/plain text/css application/json application/javascript text/xml application/xml application/xml+rss text/javascript;
}
- 设置符号链接`sudo ln -s /etc/nginx/sites-available/static-site.conf /etc/nginx/sites-enabled/`

重启nginx sudo nginx -t && sudo systemctl reload nginx

坑
本来打算用nginx做为动态转发，服务器后台跑个zola serve，结果发现zola build出来的都有端口ip:1111/xxx. 此路不通
然后就用静态网页。最开始有403，权限问题。然后发现博客的url链接是ip/ip/xxx, 用zola build -u ""可以处理掉。然后就OK啦

之前用hexo，但图片上传太麻烦了:( zola图片上传也没有那么方便。
ai真好用，特别是这种琐碎的安装部署。

rpo

2026-04-28T00:00:00.000Z

这里首先需要区分下树和图的遍历，只考虑dfs方式

树

以二叉树为例子：
dfs有pre-order，in-order，post-order。

图

只考虑有向图，一个start节点

拓扑排序

考虑到图可能存在环，问题会有些复杂。

先考虑拓扑排序，有两种情况

DAG情况（无环），不断删除入度为0的节点或者用 reverse post order方式。


图1:
    Entry
    /    \
    A    B
    \   /
    Exit

pre-order: [Entry, A, Exit, B]
post-order: [Exit, A, B, Entry]
reverse-post-order（RPO）：[Entry, B, A, Exit]就是这个DAG的拓扑排序。

RPO还是和pre-order不一样的。

有环（loop）：其实就没拓扑排序的概念了，这个循环是绕不开的。

图2:
        Entry
          │
          ▼
          A ◄────┐
        ↙   ↘    │
       B     C   │
       │     │   │
       │     ▼   │
       │     D   │
       │     │   │
       │     ▼   │
       │     E   │
        ↘   ↙    │
          F ─────┘ (back edge F → A)
          │
          ▼
         Exit

pre-order: [Entry, A, B, F, Exit, C, D, E]
post-order: [Exit, F, B, E, D, C, A, Entry]
reverser-post-order: [Entry, A, C, D, E, B, F, Exit]

数据流分析

有两种信息的流向

前向，从entry到exit，例如图2从A->B, A->C
后向，从exit到entry, 例如图2从B->A, C->A

对于图1，一次RPO就能完成前向分析。对于图2，一次RPO不能迭代到不动点，所以还是需要多次迭代。
至于后向分析，有两种思路1.对原图进行post order；2.对源图求逆，然后进行rpo1。

图3:

A  --> B --> D
      | ^
      v |
       C


---------------------

图4：

A  <-- B <--- D
      ^ |
      | v
       C

图4是图3的逆,
对图3进行post-order：D，C，B，A。
对图4进行RPO：D，B，C，A

性能

不管前向后向，顺序遍历肯定是可行方法。

bool changed = false;
do{
    chaneged = false;
    for(auto block: func) {
        changed |= ...
    }
}while(changed)

对于前向分析，DAG情况下RPO肯定块，loop情况下我没实测过，但考虑到分支众多，RPO应该比顺序遍历要快吧。
逆向分析下，我也没测试过。。。

参考

https://eli.thegreenplace.net/2015/directed-graph-traversal-orderings-and-applications-to-data-flow-analysis/

书籍阅读

2026-04-22T00:00:00.000Z

体系结构

计算机体系结构量化研究方法

编译器相关

比较推荐的书

高级编译器设计与实现 (鲸书)
ssa based compiler design
深入理解llvm代码生成 (彭成寒等著)
LLVM Code Generation A deep dive into compiler backend development (Quentin Colombet)
编译器设计 (Engineering a Compiler)
https://gcc.godbolt.org/ https://alive2.llvm.org/ce/
龙书：大而全，前端太多了，导致后端没耐心看了，其实后端优化写的挺好的

次一级的书

虎书：之前买过一本，感觉越后面越糊
llvm cookbook：入门书

机器无关优化看鲸书和编译器设计。至于优化的具体实现，llvm+ai。论文一般都很老了，快速看看就行。

TODO

Nonlinear Dynamics And Chaos

tablegen

2026-04-22T00:00:00.000Z

0

构建llvm-tblgen， cmake configure后 cd build && ninja llvm-tblgen
查看tblgen对某个td文件的实际命令：在build.ninja里面搜索。
比如说 X86GenAsmMatcher.inc是怎么编译出来的.


# Custom command for lib\Target\X86\X86GenAsmMatcher.inc

build lib/Target/X86/X86GenAsmMatcher.inc | ${cmake_ninja_workdir}lib/Target/X86/X86GenAsmMatcher.inc: CUSTOM_COMMAND bin/llvm-tblgen.exe bin/llvm-tblgen.exe D$:/Code/llvm-project/llvm/lib/Target/X86/X86.td || bin/llvm-min-tblgen.exe bin/llvm-tblgen.exe include/llvm/CodeGen/vt_gen include/llvm/IR/intrinsics_gen lib/LLVMCodeGenTypes.lib lib/LLVMDemangle.lib lib/LLVMSupport.lib lib/LLVMTableGen.lib lib/Support/BLAKE3/LLVMSupportBlake3 utils/TableGen/Basic/obj.LLVMTableGenBasic utils/TableGen/Common/obj.LLVMTableGenCommon
  COMMAND = C:\WINDOWS\system32\cmd.exe /C "cd /D D:\Code\llvm-project\build\lib\Target\X86 && D:\Code\llvm-project\build\bin\llvm-tblgen.exe -gen-asm-matcher -ID:/Code/llvm-project/llvm/lib/Target/X86 -ID:/Code/llvm-project/build/include -ID:/Code/llvm-project/llvm/include -I D:/Code/llvm-project/llvm/lib/Target D:/Code/llvm-project/llvm/lib/Target/X86/X86.td --write-if-changed -o X86GenAsmMatcher.inc -d X86GenAsmMatcher.inc.d && "D:\Program Files\bin\cmake.exe" -E cmake_transform_depfile Ninja gccdepfile D:/Code/llvm-project/llvm D:/Code/llvm-project/llvm/lib/Target/X86 D:/Code/llvm-project/build D:/Code/llvm-project/build/lib/Target/X86 D:/Code/llvm-project/build/lib/Target/X86/X86GenAsmMatcher.inc.d D:/Code/llvm-project/build/CMakeFiles/d/c78dca343be67cfabd341efa9fb0fbe70dafdeceb081e5cb7ee12866c0dd9055.d"
  DESC = Building X86GenAsmMatcher.inc...
  depfile = CMakeFiles\d\c78dca343be67cfabd341efa9fb0fbe70dafdeceb081e5cb7ee12866c0dd9055.d
  deps = gcc
  restat = 1

实际的命令就是D:/Code/llvm-project/build/bin/llvm-tblgen.exe -gen-asm-matcher -ID:/Code/llvm-project/llvm/lib/Target/X86 -ID:/Code/llvm-project/build/include -ID:/Code/llvm-project/llvm/include -I D:/Code/l lvm-project/llvm/lib/Target D:/Code/llvm-project/llvm/lib/Target/X86/X86.td --write-if-changed -o X86GenAsmMatcher.inc. -gen-asm-matcher就是生成具体代码实现。

生成record：删除掉-gen-asm-matcher就行。record文件巨大会卡。

1. Basic

基本流程 .td —> records —> .inc

class，def

class：和cpp里的类差不多,定义一个类型
def：一个record实例，类似定义一个cpp变量


class A{
string fromA = "From A";
}
class B {
int num = 10;
}

def X0: A, B{}
def X1: A, B{}

结果是：

------------- Classes -----------------
class A {
  string fromA = "From A";
}
class B {
  int num = 10;
}
------------- Defs -----------------
def X0 {        // A B
  string fromA = "From A";
  int num = 10;
}
def X1 {        // A B
  string fromA = "From A";
  int num = 10;
}

record的member必须有类型，内建类型有int, string, bits, bits, list, dag，自定义类型就是class了

multiclass,defm

multiclass就是多个record，而不是类型。defm一次定义多个record。

class Inst{
    string name = n;
    int price = p;
}

multiclass Bundle {
def A: Inst;
def B: Inst;
def C {
string name = !strconcat(base, "-", "C");
string tag = "special";
}
}

class ShippingPrice {
int shippingPrice = arg;
}
defm valuedBundle : Bundle<"valued">, ShippingPrice<5>;

def AnotherRecord {
list gifts = [valuedBundleA, valuedBundleB];
list ps = [valuedBundleA, valuedBundleB];
}

------------- Classes -----------------
class Inst {
  string name = Inst:n;
  int price = Inst:p;
}
class ShippingPrice {
  int shippingPrice = ShippingPrice:arg;
}
------------- Defs -----------------
def AnotherRecord {
  list gifts = [valuedBundleA, valuedBundleB];
  list ps = [valuedBundleA, valuedBundleB];
}
def valuedBundleA {     // Inst ShippingPrice
  string name = "valued-A";
  int price = 1;
  int shippingPrice = 5;
}
def valuedBundleB {     // Inst ShippingPrice
  string name = "valued-B";
  int price = 2;
  int shippingPrice = 5;
}
def valuedBundleC {     // ShippingPrice
  string name = "valued-C";
  string tag = "special";
  int shippingPrice = 5;
}

let绑定

注意顺序。

class MyClass {
string alias = _alias;
}
let alias = "let from out" in
def A: MyClass<> {}
def B: MyClass<> {
let alias = "let from body";
}
def C: MyClass<"from arg">;
let alias = "alias from bigger scope" in {
let alias = "let from out" in
def D: MyClass<"from arg"> {
let alias = "let from body";
}
def E: MyClass<"will be overridden">;
} // end "alias from bigger scope"

def F:MyClass<"from arg">{
    let alias = "let From body";
}
let alias = "let from Out" in
    def G:MyClass<"from arg">{}

------------- Classes -----------------
class MyClass {
  string alias = MyClass:_alias;
}
------------- Defs -----------------
def A { // MyClass
  string alias = "let from out";
}
def B { // MyClass
  string alias = "let from body";
}
def C { // MyClass
  string alias = "from arg";
}
def D { // MyClass
  string alias = "let from body";
}
def E { // MyClass
  string alias = "alias from bigger scope";
}
def F { // MyClass
  string alias = "let From body";
}
def G { // MyClass
  string alias = "let from Out";
}

2. Backend

clang-tblgen, llvm-tblgen, mlir-tblgen

[WIP]基础cuda

2026-04-13T00:00:00.000Z

线程组织 grid，block，thread。
一个kernel启动的所有线程称为grid。block是调度单元。<<<网格大小，线程块大小>>>
实际硬件：GPU，SM （stream multiprocessor），SP。
SM： local register file + shared memory+L1 cache+ a number of functional units that perform computations
一个block的所有thread都在一个SM上执行。

CUDA要求以任意顺序执行blocks，即一个thread block不应该依赖其他block（同grid）。

warp
block内部，threads以32个为一warp组织起来。warp是以SIMT模型执行kernel。该warp的线程执行相同的kernel code，但可以有不同branch。
When different threads in a warp follow different code paths, this is sometimes called warp divergence。
内存层次
- DRAM，global memory 可被所有块所有线程访问， HBM
  coalesced global memory access：
  global memory以32bytes为单位访问称为memory transaction。
  warp会将内部线程的内存访问映射为memory transactions。
- 同一个block内的线程访问，on chip memory，每个SM独占的。
  - shared memory
    32banks x 32bits/cycle
    bank confilct：multi threads in the same warp attempt to access different elements in the same bank.
  - L1 cache
  - register file
    如果某个thread block需要的寄存器大于寄存器个数，该kernel不可启动
  - 常量内存
- local memory 每个thread独有的。实际上在global memory上面。
  - 特别是register spilling
thread hierarchy

The threads of a block are linearized predictably: the first index x moves the fastest,
followed by y and then z. This means that in the linearization of a thread indices, consecutive values of threadIdx.x indicate consecutive threads, threadIdx.y has a stride of blockDim.x, and threadIdx.z has a stride of blockDim.x * blockDim.y.

linear_id = threadIdx.x + threadIdx.y * blockDim.x + threadId.z * blockDim.x * blockDim.y

从threadid到 memory address的方式是自己选择的。

__global__ void transpose_shared(float* out, const float* in, int w, int h) {

    __shared__ float tile[TILE][TILE + 1];  // +1 避免 bank conflict

    // ===== 1. 全局坐标 =====
    int x = blockIdx.x * TILE + threadIdx.x;
    int y = blockIdx.y * TILE + threadIdx.y;

    // ===== 2. global → shared（连续读）=====
    if (x < w && y < h) {
        tile[threadIdx.y][threadIdx.x] = in[y * w + x];
    }

    __syncthreads();

    // ===== 3. 交换 blockIdx（关键！！！）=====
    int new_x = blockIdx.y * TILE + threadIdx.x;
    int new_y = blockIdx.x * TILE + threadIdx.y;

    // ===== 4. shared → global（连续写）=====
    if (new_x < h && new_y < w) {
        out[new_y * h + new_x] = tile[threadIdx.x][threadIdx.y];
    }
}

[WIP]mlir

2026-04-13T00:00:00.000Z

学习下mlir

1. 基本概念

树形结构。Op，Region，Block，Op
使用基本块参数代替phi
Operand结构
1. 操作
2. 返回值：OpResult
3. regions
4. attrDict，属性字典
5. 参数：OpOperand, 经典的Use结构
Value是ValueImpl*的包装，type+kind
Type, TypeStorage* 实际上是AbstractType* = {dialect, interface, typeid,name, subtypes}
interface vs trait
- interface想要语义描述和具体Op/dialect解耦, 给pass提供api
  使用主要是
  1
  2
  3
  4
  5
  Dialect *dialect = ...;
  if (DialectInlinerInterface *interface = dyn_cast(dialect)) {
  // The dialect has provided an implementation of this interface.
  ...
  }
- trait 更加静态，为attrs/ops/types 提供公共信息，比如说side effects
  Operation *op = ..; if (op->hasTrait()) ...

2. 添加dialect

3. 添加pass

4. pattern rewriter

5. converter

ref

https://github.com/KEKE046/mlir-tutorial

mlir构建

2026-04-13T00:00:00.000Z

以mac air构建为例，耗时26min。


cmake -G Ninja \
    -DCMAKE_EXPORT_COMPILE_COMMANDS=ON  \
    -S ./llvm -B build \
    -DCMAKE_BUILD_TYPE=RELWITHDEBINFO \
    -DLLVM_BUILD_EXAMPLES=ON \
    -DLLVM_ENABLE_PROJECTS="mlir" \
    -DLLVM_TARGETS_TO_BUILD="Native;NVPTX" \
    -DLLVM_ENABLE_ASSERTIONS=ON

cd build && ninja

把mlir当作lib使用

需要构建mlir
cmake配置


set -x

mkdir -p build
cd build
cmake .. -GNinja -DCMAKE_INSTALL_PREFIX=//install  -DCMAKE_PREFIX_PATH=../build
ninja

GVN-PRE简介

2026-04-08T00:00:00.000Z

参考 https://cs.wheaton.edu/~tvandrun/writings/cc04.pdf
只考虑表达式，基于SSA

GVN是将Global value numbering，而PRE是Partial redundancy elimination。一个是值编号，一个是部分冗余消除。

GVN的思路简单，按照domtree进行深度优先遍历，记录每个block中表达式的编号，如果重复就删除重复的。
对如下ir

define i32 @foo(i32 %a, i32 %cond){
bb0:
    %add = add i32 %a, %a
    %c = icmp eq %cond, 0
    br %c, %bb1, %bb2
bb1:
    %a2 = add i32 %a, %a
    br %bb3

bb2:
    %a3 = add i32 %a, 1
    br %bb3
bb3:
    %phia = phi(%a2, %a3)
    ret i32 %phia
}

按照domtree进行遍历，bb0,bb1,bb2,bb3，有以下结果。
%a: v0
%cond: v1
%add: v2
%c: v3
%a2: v2 (same as %add)
%a3: v4
%phia: v5

所以说%a2是冗余的值，可以删除掉。

PRE更加复杂一些。

在这个例子2里面，%sa和%a2重复，但bb1不dom bb3. 单纯GVN没法处理。

define i32 @bar(i32 %a, i32 %cond){
bb0:
    %c = icmp eq %cond, 0
    br %c, %bb1, %bb2
bb1:
    %a2 = add i32 %a, %a
    br %bb3

bb2:
    %a3 = add i32 %a, 3
    br %bb3
bb3:
    %phia = phi(%a2, %a3)
    %sa = add i32 %a, %a
    ret i32 %phia
}

PRE的算法有些复杂，这里先不介绍了。

GVN-PRE

结合二者的优点，GVN简单，PRE能力强。
针对上面的例子2，如果用逆向数据流分析，将%sa从bb3放到bb0底部，那么也就能消除%a2了。

不过首先需要确定可用集合。就是在每个block最后，有哪些表达式可用。
还是按照GVN的思路，根据domtree遍历。
所以数据流公式就是

AVAIL_IN[b] = AVAIL_OUT[dom(b)]
AVAIL_OUT[b] = AVAIL_IN[b] U PHI_GEN[b] U TMP_EXP[b]

PHI_GEN就是phinode，TMP_EXP是b中定义的非phi节点。

然后因为需要逆向数据流分析（回想下liveness），所以

ANTIC_OUT[b] = 
    - for i in succ(b) { ∧ ANTIC_IN[i] } if |succ(b)| > 1
    - phi_translate( ANTIC_IN[succ(b)] ) if |succ(b)| =1

ANTIC_IN[b] = clean(ANTIC_OUT[b] U EXP_GEN[b] - TMP_GEN[b])


EXP_GEN就是value和指令右侧表达式的集合。
clean会删除掉依赖被killed的值

所以算法就是

计算avail和antic集合
处理hoist
for b in blocks{
if preds(b) < 2
continue
for e in ANTIC_IN[b]:
if e is avaiable in at least one predcessor, then insert e into predecessors where not avaiable.
}
(还有sink和hoist相反，原理类似)
删除冗余表达式

llvm寄存器分配2

2026-03-22T00:00:00.000Z

greedy

TODO

llvm寄存器分配1

2026-03-22T00:00:00.000Z

接上一篇。
列举下RABasic需要的数据结构

LiveRegMatrix， LiveIntervals， VirtRegMap， LiveIntervalUnion
LiveIntervals

核心的查询接口。

VirtRegIntervals Map
RegMaskSlots 是用来储存哪些指令用了regmask（基本是call），在判断干涉时用到，按照slotindex排序
RegMaskBits，查询的cache
RegMaskBlocks： Map 这里的begin是RegMaskSlots的下标，即某个block对应哪些使用regmask的指令


class LiveIntervals {
  MachineFunction *MF = nullptr;
  MachineRegisterInfo *MRI = nullptr;
  const TargetRegisterInfo *TRI = nullptr;
  const TargetInstrInfo *TII = nullptr;
  SlotIndexes *Indexes = nullptr;
  MachineDominatorTree *DomTree = nullptr;
  std::unique_ptr LICalc;

  /// Live interval pointers for all the virtual registers.
  IndexedMap VirtRegIntervals;

  /// Sorted list of instructions with register mask operands. Always use the
  /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
  SmallVector8> RegMaskSlots;

  /// This vector is parallel to RegMaskSlots, it holds a pointer to the
  /// corresponding register mask.  This pointer can be recomputed as:
  ///
  ///   MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
  ///   unsigned OpNum = findRegMaskOperand(MI);
  ///   RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
  ///
  /// This is kept in a separate vector partly because some standard
  /// libraries don't support lower_bound() with mixed objects, partly to
  /// improve locality when searching in RegMaskSlots.
  /// Also see the comment in LiveInterval::find().
  SmallVector<const uint32_t *, 8> RegMaskBits;

  /// For each basic block number, keep (begin, size) pairs indexing into the
  /// RegMaskSlots and RegMaskBits arrays.
  /// Note that basic block numbers may not be layout contiguous, that's why
  /// we can't just keep track of the first register mask in each basic
  /// block.
  SmallVectorunsigned, unsigned>, 8> RegMaskBlocks;

  /// Keeps a live range set for each register unit to track fixed physreg
  /// interference.
  SmallVector0> RegUnitRanges;
}

LiveIntervalUnion， llvm/include/llvm/CodeGen/LiveIntervalUnion.h
IntervalMap的包装类。


class LiveIntervalUnion{

  IntervalMapconst LiveInterval *> Segments;

  class Array {
    unsigned Size = 0;
    LiveIntervalUnion *LIUs = nullptr;
  }
};

LiveRegMatrix

llvm/include/llvm/CodeGen/LiveRegMatrix.h

用来追踪虚拟寄存器的干涉情况，是一个二维结构， slot index x reg units.

用LiveIntervalUnion::Array Matrix;表示这个二维结构.
InterferenceKind作为干涉查询结果。InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
- IK_Free 没干涉
- IK_VirtReg，虚拟寄存器和物理寄存器干涉。
- IK_RegUnit, 不太清楚
- IK_RegMask，主要是call里面的regmask


class LiveRegMatrix : public MachineFunctionPass {
  const TargetRegisterInfo *TRI = nullptr;
  LiveIntervals *LIS = nullptr;
  VirtRegMap *VRM = nullptr;

  // UserTag changes whenever virtual registers have been modified.
  unsigned UserTag = 0;

  // The matrix is represented as a LiveIntervalUnion per register unit.
  LiveIntervalUnion::Array Matrix;

  // Cached queries per register unit.
  std::unique_ptr Queries;

  // Cached register mask interference info.
  unsigned RegMaskTag = 0;
  unsigned RegMaskVirtReg = 0;
  BitVector RegMaskUsable;

public:
  enum InterferenceKind {
    /// No interference, go ahead and assign.
    IK_Free = 0,

    /// Virtual register interference. There are interfering virtual registers
    /// assigned to PhysReg or its aliases. This interference could be resolved
    /// by unassigning those other virtual registers.
    IK_VirtReg,

    /// Register unit interference. A fixed live range is in the way, typically
    /// argument registers for a call. This can't be resolved by unassigning
    /// other virtual registers.
    IK_RegUnit,

    /// RegMask interference. The live range is crossing an instruction with a
    /// regmask operand that doesn't preserve PhysReg. This typically means
    /// VirtReg is live across a call, and PhysReg isn't call-preserved.
    IK_RegMask
  };

  /// Check for interference before assigning VirtReg to PhysReg.
  /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
  /// When there is more than one kind of interference, the InterferenceKind
  /// with the highest enum value is returned.
  InterferenceKind checkInterference(const LiveInterval &VirtReg,
                                     MCRegister PhysReg);

  /// Check for interference in the segment [Start, End) that may prevent
  /// assignment to PhysReg. If this function returns true, there is
  /// interference in the segment [Start, End) of some other interval already
  /// assigned to PhysReg. If this function returns false, PhysReg is free at
  /// the segment [Start, End).
  bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);

  /// Assign VirtReg to PhysReg.
  /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
  /// update VirtRegMap. The live range is expected to be available in PhysReg.
  void assign(const LiveInterval &VirtReg, MCRegister PhysReg);

  /// Unassign VirtReg from its PhysReg.
  /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
  /// the assignment and updates VirtRegMap accordingly.
  void unassign(const LiveInterval &VirtReg);

  /// Returns true if the given \p PhysReg has any live intervals assigned.
  bool isPhysRegUsed(MCRegister PhysReg) const;

  //===--------------------------------------------------------------------===//
  // Low-level interface.
  //===--------------------------------------------------------------------===//
  //
  // Provide access to the underlying LiveIntervalUnions.
  //

  /// Check for regmask interference only.
  /// Return true if VirtReg crosses a regmask operand that clobbers PhysReg.
  /// If PhysReg is null, check if VirtReg crosses any regmask operands.
  bool checkRegMaskInterference(const LiveInterval &VirtReg,
                                MCRegister PhysReg = MCRegister::NoRegister);

  /// Check for regunit interference only.
  /// Return true if VirtReg overlaps a fixed assignment of one of PhysRegs's
  /// register units.
  bool checkRegUnitInterference(const LiveInterval &VirtReg,
                                MCRegister PhysReg);

  /// Query a line of the assigned virtual register matrix directly.
  /// Use MCRegUnitIterator to enumerate all regunits in the desired PhysReg.
  /// This returns a reference to an internal Query data structure that is only
  /// valid until the next query() call.
  LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);

  /// Directly access the live interval unions per regunit.
  /// This returns an array indexed by the regunit number.
  LiveIntervalUnion *getLiveUnions() { return &Matrix[0]; }

  Register getOneVReg(unsigned PhysReg) const;
};

vregmap, rewriter时候使用
即寄存器分配的内容不是立即改写mir，而是在rewriter pass时候才会改写mir。


class VirtRegMap : public MachineFunctionPass {
  MachineRegisterInfo *MRI = nullptr;
  const TargetInstrInfo *TII = nullptr;
  const TargetRegisterInfo *TRI = nullptr;
  MachineFunction *MF = nullptr;

  /// Virt2PhysMap - This is a virtual to physical register
  /// mapping. Each virtual register is required to have an entry in
  /// it; even spilled virtual registers (the register mapped to a
  /// spilled register is the temporary used to load it from the
  /// stack).
  IndexedMap Virt2PhysMap;

  /// Virt2StackSlotMap - This is virtual register to stack slot
  /// mapping. Each spilled virtual register has an entry in it
  /// which corresponds to the stack slot this register is spilled
  /// at.
  IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;

  /// Virt2SplitMap - This is virtual register to splitted virtual register
  /// mapping.
  IndexedMap Virt2SplitMap;

  /// Virt2ShapeMap - For X86 AMX register whose register is bound shape
  /// information.
  DenseMap Virt2ShapeMap;
};

regalloc 算法实现

regalloc base

llvm/lib/CodeGen/RegAllocBase.cpp

线性扫描+优先队列的思路.
该文件里定义了一系列接口
RegAllocBase 核心是: enqueueImpl, dequeue, selectOrSplit


class RegAllocBase {
  virtual void anchor();
protected:
  const TargetRegisterInfo *TRI = nullptr;
  MachineRegisterInfo *MRI = nullptr;
  VirtRegMap *VRM = nullptr;
  LiveIntervals *LIS = nullptr;
  LiveRegMatrix *Matrix = nullptr;
  RegisterClassInfo RegClassInfo;

private:
  /// Private, callees should go through shouldAllocateRegister
  const RegAllocFilterFunc shouldAllocateRegisterImpl;
protected:
  /// Inst which is a def of an original reg and whose defs are already all
  /// dead after remat is saved in DeadRemats. The deletion of such inst is
  /// postponed till all the allocations are done, so its remat expr is
  /// always available for the remat of all the siblings of the original reg.
  SmallPtrSet32> DeadRemats;


  // The top-level driver. The output is a VirtRegMap that us updated with
  // physical register assignments.
  void allocatePhysRegs();

  // Include spiller post optimization and removing dead defs left because of
  // rematerialization.
  virtual void postOptimization();

  // Get a temporary reference to a Spiller instance.
  virtual Spiller &spiller() = 0;

  virtual void enqueueImpl(const LiveInterval *LI) = 0;

  /// enqueue - Add VirtReg to the priority queue of unassigned registers.
  void enqueue(const LiveInterval *LI);

  /// dequeue - Return the next unassigned register, or NULL.
  virtual const LiveInterval *dequeue() = 0;

  virtual MCRegister selectOrSplit(const LiveInterval &VirtReg,
                                   SmallVectorImpl &splitLVRs) = 0;
};

// 结构精简后:
void RegAllocBase::allocatePhysRegs(){
    while (const LiveInterval *VirtReg = dequeue()) {
        VirtRegVec SplitVRegs;
        MCRegister AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
        if(AvailablePhysReg == ~0u){
            report_error
        }else if (AvailablePhysReg){
            Matrix->assign(*VirtReg, AvailablePhysReg);
        }
        for (Register Reg : SplitVRegs) {

            LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);

            enqueue(SplitVirtReg);
            ++NumNewQueued;
        }
    }
}

RegAllocBasic

llvm/lib/CodeGen/RegAllocBasic.cpp
很简易的实现. 还是先看selectOrSplit的实现

先检测有没有可用物理寄存器。有就直接返回
没有则尝试将更低weight的已分配寄存器溢出
还是不行就将自己溢出。


void enqueueImpl(const LiveInterval *LI) override { Queue.push(LI); }
const LiveInterval *dequeue() override {
  if (Queue.empty())
    return nullptr;
  const LiveInterval *LI = Queue.top();
  Queue.pop();
  return LI;
}

MCRegister RABasic::selectOrSplit(const LiveInterval &VirtReg,
                                  SmallVectorImpl &SplitVRegs) {
  // Populate a list of physical register spill candidates.
  SmallVector8> PhysRegSpillCands;

  // Check for an available register in this class.
  auto Order =
      AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
  for (MCRegister PhysReg : Order) {
    assert(PhysReg.isValid());
    // Check for interference in PhysReg
    switch (Matrix->checkInterference(VirtReg, PhysReg)) {
    case LiveRegMatrix::IK_Free:
      // PhysReg is available, allocate it.
      return PhysReg;

    case LiveRegMatrix::IK_VirtReg:
      // Only virtual registers in the way, we may be able to spill them.
      PhysRegSpillCands.push_back(PhysReg);
      continue;

    default:
      // RegMask or RegUnit interference.
      continue;
    }
  }

  // Try to spill another interfering reg with less spill weight.
  for (MCRegister &PhysReg : PhysRegSpillCands) {
    if (!spillInterferences(VirtReg, PhysReg, SplitVRegs))
      continue;

    assert(!Matrix->checkInterference(VirtReg, PhysReg) &&
           "Interference after spill.");
    // Tell the caller to allocate to this newly freed physical register.
    return PhysReg;
  }

  // No other spill candidates were found, so spill the current VirtReg.
  LLVM_DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
  if (!VirtReg.isSpillable())
    return ~0u;
  LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
  spiller().spill(LRE);

  // The live virtual register requesting allocation was spilled, so tell
  // the caller not to allocate anything during this round.
  return 0;
}

llvm寄存器分配0

2026-03-22T00:00:00.000Z

依赖的分析

value number
live range(liveness). 这块挺复杂的.
machine dom tree/machine loop
block frequency

value number

VNInfo 能处理ssa和non-ssa格式的mir

一个例子：

; llc %s -march=aarch64 --stop-after=register-coalescer 

declare void @print(i32);

define i32 @foo(i32 %a, i1 %c) {

bb0:
    br i1 %c, label %bb1, label %bb2
bb1:
    call void @print(i32 %a)
    br label %bb3

bb2:
    %a2 = add i32 %a, 1
    br label %bb3
bb3:
    %a3 = phi i32 [%a, %bb1], [%a2, %bb2]
    ret i32 %a3
}

; llc -march=aarch64 --start-after=register-coalescer -debug-only=regalloc -O1 %s
bb.0.bb0:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $w0, $w1
  
    %3:gpr32 = COPY $w1
    %5:gpr32common = COPY $w0
    TBZW %3, 0, %bb.2
    B %bb.1
  
  bb.2.bb2:
    successors: %bb.3(0x80000000)
  
    %5:gpr32common = ADDWri %5, 1, 0
    B %bb.3

  bb.1.bb1:
    successors: %bb.3(0x80000000)
  
    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
    $w0 = COPY %5
    BL @print, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp
    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
    B %bb.3

  bb.3.bb3:
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...

可以看到live intervals信息：

W0 [0B,32r:0)[160r,176r:2)[240r,256r:1) 0@0B-phi 1@240r 2@160r
W1 [0B,16r:0) 0@0B-phi
%3 [16r,48r:0) 0@16r  weight:0.000000e+00
%5 [32r,96r:1)[96r,128B:0)[128B,224B:1)[224B,240r:2) 0@96r 1@32r 2@224B-phi  weight:0.000000e+00
Function Live Ins: $w0 in %2, $w1 in %3

0Bbb.0.bb0:
  successors: %bb.2(0x40000000), %bb.1(0x40000000); %bb.2(50.00%), %bb.1(50.00%)
  liveins: $w0, $w1
16B  %3:gpr32 = COPY $w1
32B  %5:gpr32common = COPY $w0
48B  TBZW %3:gpr32, 0, %bb.1
64B  B %bb.2

80Bbb.1.bb2:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

96B  %5:gpr32common = ADDWri %5:gpr32common, 1, 0
112B  B %bb.3

128Bbb.2.bb1:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

144B  ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
160B  $w0 = COPY %5:gpr32common
176B  BL @print, , implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp
192B  ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
208B  B %bb.3

224Bbb.3.bb3:
; predecessors: %bb.1, %bb.2

240B  $w0 = COPY %5:gpr32common
256B  RET_ReallyLR implicit $w0

可以看到%5 [32r,96r:1)[96r,128B:0)[128B,224B:1)[224B,240r:2) 0@96r 1@32r 2@224B-phi，就是phi所占用的live range。
由此，live intervals实现了精细的reaching define和liveness信息构建，这也是后续regalloc的基础。

例子:

// clang a.c -O1 -mllvm -debug-only=regalloc
// x64
extern int foo(int);

int bar(int a, int b) {
    if(a>b) {
       a = foo(a) +  a*b;
         
    }else{
        a = foo(a)*foo(a) + b;
    }
    return a*(b-a);
}

输出


Computing live-in reg-units in ABI blocks.
0B%bb.0 DIL#0 DIH#0 HDI#0 SIL#0 SIH#0 HSI#0
Created 6 new intervals.
********** INTERVALS **********
DIL [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
DIH [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
HDI [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
SIL [0B,16r:0) 0@0B-phi
SIH [0B,16r:0) 0@0B-phi
HSI [0B,16r:0) 0@0B-phi
%1 [224r,240r:0)[240r,256r:1) 0@224r 1@240r  weight:0.000000e+00
%2 [416r,432r:0)[432r,448r:1) 0@416r 1@432r  weight:0.000000e+00
%3 [480r,544r:0) 0@480r  weight:0.000000e+00
%4 [32r,192r:0)[288B,320r:0) 0@32r  weight:0.000000e+00
%5 [16r,496r:0) 0@16r  weight:0.000000e+00
%6 [112r,224r:0)[288B,400r:0) 0@112r  weight:0.000000e+00
%8 [368r,384r:0) 0@368r  weight:0.000000e+00
%9 [384r,400r:0)[400r,416r:1) 0@384r 1@400r  weight:0.000000e+00
%10 [192r,208r:0)[208r,240r:1) 0@192r 1@208r  weight:0.000000e+00
%11 [496r,512r:0)[512r,528r:1) 0@496r 1@512r  weight:0.000000e+00
%12 [528r,544r:0)[544r,560r:1) 0@528r 1@544r  weight:0.000000e+00
%13 [256r,288B:1)[448r,464B:0)[464B,480r:2) 0@448r 1@256r 2@464B-phi  weight:0.000000e+00
RegMasks: 80r 336r
********** MACHINEINSTRS **********
# Machine code for function bar: NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $edi in %4, $esi in %5

0Bbb.0.entry:
  successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%), %bb.2(50.00%)
  liveins: $edi, $esi
  DBG_VALUE $edi, $noreg, !"a", !DIExpression(), debug-location !22; example.c:0 line no:50
  DBG_VALUE $esi, $noreg, !"b", !DIExpression(), debug-location !22; example.c:0 line no:50
16B  %5:gr32 = COPY $esi
32B  %4:gr32 = COPY $edi
48B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
64B  $edi = COPY %4:gr32, debug-location !25; example.c:0
80B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !25; example.c:0
96B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
112B  %6:gr32 = COPY killed $eax, debug-location !25; example.c:0
128B  CMP32rr %4:gr32, %5:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
144B  JCC_1 %bb.2, 14, implicit killed $eflags, debug-location !26; example.c:51:9
160B  JMP_1 %bb.1, debug-location !26; example.c:51:9

176Bbb.1.if.then:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

192B  %10:gr32 = COPY %4:gr32, debug-location !27; example.c:52:23
208B  %10:gr32 = nsw IMUL32rr %10:gr32(tied-def 0), %5:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
224B  %1:gr32 = COPY %6:gr32, debug-location !29; example.c:52:19
240B  %1:gr32 = nsw ADD32rr %1:gr32(tied-def 0), %10:gr32, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
  DBG_INSTR_REF !"a", !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !22; example.c:0 line no:50
256B  %13:gr32 = COPY %1:gr32
272B  JMP_1 %bb.3, debug-location !30; example.c:54:5

288Bbb.2.if.else:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

304B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
320B  $edi = COPY %4:gr32, debug-location !31; example.c:55:20
336B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31; example.c:55:20
352B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
368B  %8:gr32 = COPY killed $eax, debug-location !31; example.c:55:20
384B  %9:gr32 = COPY %8:gr32, debug-location !33; example.c:55:19
400B  %9:gr32 = nsw IMUL32rr %9:gr32(tied-def 0), %6:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
416B  %2:gr32 = COPY %9:gr32, debug-location !34; example.c:55:27
432B  %2:gr32 = nsw ADD32rr %2:gr32(tied-def 0), %5:gr32, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
  DBG_INSTR_REF !"a", !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !22; example.c:0 line no:50
448B  %13:gr32 = COPY %2:gr32

464Bbb.3.if.end:
; predecessors: %bb.2, %bb.1

480B  %3:gr32 = COPY %13:gr32, debug-location !25; example.c:0
  DBG_INSTR_REF !"a", !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !22; example.c:0 line no:50
496B  %11:gr32 = COPY %5:gr32, debug-location !35; example.c:57:16
512B  %11:gr32 = nsw SUB32rr %11:gr32(tied-def 0), %3:gr32, implicit-def dead $eflags, debug-location !35; example.c:57:16
528B  %12:gr32 = COPY %11:gr32, debug-location !36; example.c:57:13
544B  %12:gr32 = nsw IMUL32rr %12:gr32(tied-def 0), %3:gr32, implicit-def dead $eflags, debug-location !36; example.c:57:13
560B  $eax = COPY %12:gr32, debug-location !37; example.c:57:5
576B  RET 0, killed $eax, debug-location !37; example.c:57:5

# End machine code for function bar.

********** REGISTER COALESCER **********
********** Function: bar
********** JOINING INTERVALS ***********
entry:
16B%5:gr32 = COPY $esi
Considering merging %5 with $esi
Can only merge into reserved registers.
32B%4:gr32 = COPY $edi
Considering merging %4 with $edi
Can only merge into reserved registers.
64B$edi = COPY %4:gr32, debug-location !25; example.c:0
Considering merging %4 with $edi
Can only merge into reserved registers.
112B%6:gr32 = COPY killed $eax, debug-location !25; example.c:0
Considering merging %6 with $eax
Can only merge into reserved registers.
if.then:
if.else:
320B$edi = COPY %4:gr32, debug-location !31; example.c:55:20
Considering merging %4 with $edi
Can only merge into reserved registers.
368B%8:gr32 = COPY killed $eax, debug-location !31; example.c:55:20
Considering merging %8 with $eax
Can only merge into reserved registers.
if.end:
560B$eax = COPY %12:gr32, debug-location !37; example.c:57:5
Considering merging %12 with $eax
Can only merge into reserved registers.
192B%10:gr32 = COPY %4:gr32, debug-location !27; example.c:52:23
AllocationOrder(GR32) = [ $eax $ecx $edx $esi $edi $r8d $r9d $r10d $r11d $ebx $ebp $r14d $r15d $r12d $r13d ]
Considering merging to GR32 with %4 in %10
RHS = %4 [32r,192r:0)[288B,320r:0) 0@32r  weight:0.000000e+00
LHS = %10 [192r,208r:0)[208r,240r:1) 0@192r 1@208r  weight:0.000000e+00
merge %10:0@192r into %4:0@32r --> @32r
erased:192r%10:gr32 = COPY %4:gr32, debug-location !27; example.c:52:23
updated: 32B%10:gr32 = COPY $edi
updated: 64B$edi = COPY %10:gr32, debug-location !25; example.c:0
updated: 128BCMP32rr %10:gr32, %5:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
updated: 320B$edi = COPY %10:gr32, debug-location !31; example.c:55:20
Success: %4 -> %10
Result = %10 [32r,208r:0)[208r,240r:1)[288B,320r:0) 0@32r 1@208r  weight:0.000000e+00
224B%1:gr32 = COPY %6:gr32, debug-location !29; example.c:52:19
Considering merging to GR32 with %6 in %1
RHS = %6 [112r,224r:0)[288B,400r:0) 0@112r  weight:0.000000e+00
LHS = %1 [224r,240r:0)[240r,256r:1) 0@224r 1@240r  weight:0.000000e+00
merge %1:0@224r into %6:0@112r --> @112r
erased:224r%1:gr32 = COPY %6:gr32, debug-location !29; example.c:52:19
updated: 112B%1:gr32 = COPY killed $eax, debug-location !25; example.c:0
updated: 400B%9:gr32 = nsw IMUL32rr %9:gr32(tied-def 0), %1:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
Success: %6 -> %1
Result = %1 [112r,240r:0)[240r,256r:1)[288B,400r:0) 0@112r 1@240r  weight:0.000000e+00
256B%13:gr32 = COPY %1:gr32
Considering merging to GR32 with %1 in %13
RHS = %1 [112r,240r:0)[240r,256r:1)[288B,400r:0) 0@112r 1@240r  weight:0.000000e+00
LHS = %13 [256r,288B:1)[448r,464B:0)[464B,480r:2) 0@448r 1@256r 2@464B-phi  weight:0.000000e+00
merge %13:1@256r into %1:1@240r --> @240r
erased:256r%13:gr32 = COPY %1:gr32
updated: 112B%13:gr32 = COPY killed $eax, debug-location !25; example.c:0
updated: 240B%13:gr32 = nsw ADD32rr %13:gr32(tied-def 0), %10:gr32, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
updated: 400B%9:gr32 = nsw IMUL32rr %9:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
Success: %1 -> %13
Result = %13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,480r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:0.000000e+00
384B%9:gr32 = COPY %8:gr32, debug-location !33; example.c:55:19
Considering merging to GR32 with %8 in %9
RHS = %8 [368r,384r:0) 0@368r  weight:0.000000e+00
LHS = %9 [384r,400r:0)[400r,416r:1) 0@384r 1@400r  weight:0.000000e+00
merge %9:0@384r into %8:0@368r --> @368r
erased:384r%9:gr32 = COPY %8:gr32, debug-location !33; example.c:55:19
updated: 368B%9:gr32 = COPY killed $eax, debug-location !31; example.c:55:20
Success: %8 -> %9
Result = %9 [368r,400r:0)[400r,416r:1) 0@368r 1@400r  weight:0.000000e+00
416B%2:gr32 = COPY %9:gr32, debug-location !34; example.c:55:27
Considering merging to GR32 with %9 in %2
RHS = %9 [368r,400r:0)[400r,416r:1) 0@368r 1@400r  weight:0.000000e+00
LHS = %2 [416r,432r:0)[432r,448r:1) 0@416r 1@432r  weight:0.000000e+00
merge %2:0@416r into %9:1@400r --> @400r
erased:416r%2:gr32 = COPY %9:gr32, debug-location !34; example.c:55:27
updated: 368B%2:gr32 = COPY killed $eax, debug-location !31; example.c:55:20
updated: 400B%2:gr32 = nsw IMUL32rr %2:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
Success: %9 -> %2
Result = %2 [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r  weight:0.000000e+00
448B%13:gr32 = COPY %2:gr32
Considering merging to GR32 with %2 in %13
RHS = %2 [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r  weight:0.000000e+00
LHS = %13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,480r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:0.000000e+00
merge %13:0@448r into %2:1@432r --> @432r
interference at %2:2@368r
Interference!
480B%3:gr32 = COPY %13:gr32, debug-location !25; example.c:0
Considering merging to GR32 with %3 in %13
RHS = %3 [480r,544r:0) 0@480r  weight:0.000000e+00
LHS = %13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,480r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:0.000000e+00
merge %3:0@480r into %13:2@464B --> @464B
erased:480r%3:gr32 = COPY %13:gr32, debug-location !25; example.c:0
updated: 512B%11:gr32 = nsw SUB32rr %11:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !35; example.c:57:16
updated: 544B%12:gr32 = nsw IMUL32rr %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !36; example.c:57:13
Success: %3 -> %13
Result = %13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:0.000000e+00
496B%11:gr32 = COPY %5:gr32, debug-location !35; example.c:57:16
Considering merging to GR32 with %5 in %11
RHS = %5 [16r,496r:0) 0@16r  weight:0.000000e+00
LHS = %11 [496r,512r:0)[512r,528r:1) 0@496r 1@512r  weight:0.000000e+00
merge %11:0@496r into %5:0@16r --> @16r
erased:496r%11:gr32 = COPY %5:gr32, debug-location !35; example.c:57:16
updated: 16B%11:gr32 = COPY $esi
updated: 128BCMP32rr %10:gr32, %11:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
updated: 432B%2:gr32 = nsw ADD32rr %2:gr32(tied-def 0), %11:gr32, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
updated: 208B%10:gr32 = nsw IMUL32rr %10:gr32(tied-def 0), %11:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
Success: %5 -> %11
Result = %11 [16r,512r:0)[512r,528r:1) 0@16r 1@512r  weight:0.000000e+00
528B%12:gr32 = COPY %11:gr32, debug-location !36; example.c:57:13
Considering merging to GR32 with %11 in %12
RHS = %11 [16r,512r:0)[512r,528r:1) 0@16r 1@512r  weight:0.000000e+00
LHS = %12 [528r,544r:0)[544r,560r:1) 0@528r 1@544r  weight:0.000000e+00
merge %12:0@528r into %11:1@512r --> @512r
erased:528r%12:gr32 = COPY %11:gr32, debug-location !36; example.c:57:13
updated: 16B%12:gr32 = COPY $esi
updated: 512B%12:gr32 = nsw SUB32rr %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !35; example.c:57:16
updated: 128BCMP32rr %10:gr32, %12:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
updated: 432B%2:gr32 = nsw ADD32rr %2:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
updated: 208B%10:gr32 = nsw IMUL32rr %10:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
Success: %11 -> %12
Result = %12 [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r  weight:0.000000e+00
64B$edi = COPY %10:gr32, debug-location !25; example.c:0
Considering merging %10 with $edi
Can only merge into reserved registers.
320B$edi = COPY %10:gr32, debug-location !31; example.c:55:20
Considering merging %10 with $edi
Can only merge into reserved registers.
448B%13:gr32 = COPY %2:gr32
Considering merging to GR32 with %2 in %13
RHS = %2 [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r  weight:0.000000e+00
LHS = %13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:0.000000e+00
merge %13:0@448r into %2:1@432r --> @432r
interference at %2:2@368r
Interference!
Trying to inflate 0 regs.
********** INTERVALS **********
DIL [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
DIH [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
HDI [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
SIL [0B,16r:0) 0@0B-phi
SIH [0B,16r:0) 0@0B-phi
HSI [0B,16r:0) 0@0B-phi
%2 [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r  weight:0.000000e+00
%10 [32r,208r:0)[208r,240r:1)[288B,320r:0) 0@32r 1@208r  weight:0.000000e+00
%12 [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r  weight:0.000000e+00
%13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:0.000000e+00
RegMasks: 80r 336r
********** MACHINEINSTRS **********
# Machine code for function bar: NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $edi in %4, $esi in %5

0Bbb.0.entry:
  successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%), %bb.2(50.00%)
  liveins: $edi, $esi
  DBG_VALUE $edi, $noreg, !"a", !DIExpression(), debug-location !22; example.c:0 line no:50
  DBG_VALUE $esi, $noreg, !"b", !DIExpression(), debug-location !22; example.c:0 line no:50
16B  %12:gr32 = COPY $esi
32B  %10:gr32 = COPY $edi
48B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
64B  $edi = COPY %10:gr32, debug-location !25; example.c:0
80B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !25; example.c:0
96B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
112B  %13:gr32 = COPY killed $eax, debug-location !25; example.c:0
128B  CMP32rr %10:gr32, %12:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
144B  JCC_1 %bb.2, 14, implicit killed $eflags, debug-location !26; example.c:51:9
160B  JMP_1 %bb.1, debug-location !26; example.c:51:9

176Bbb.1.if.then:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

208B  %10:gr32 = nsw IMUL32rr %10:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
240B  %13:gr32 = nsw ADD32rr %13:gr32(tied-def 0), %10:gr32, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
  DBG_INSTR_REF !"a", !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !22; example.c:0 line no:50
272B  JMP_1 %bb.3, debug-location !30; example.c:54:5

288Bbb.2.if.else:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

304B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
320B  $edi = COPY %10:gr32, debug-location !31; example.c:55:20
336B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31; example.c:55:20
352B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
368B  %2:gr32 = COPY killed $eax, debug-location !31; example.c:55:20
400B  %2:gr32 = nsw IMUL32rr %2:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
432B  %2:gr32 = nsw ADD32rr %2:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
  DBG_INSTR_REF !"a", !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !22; example.c:0 line no:50
448B  %13:gr32 = COPY %2:gr32

464Bbb.3.if.end:
; predecessors: %bb.2, %bb.1

  DBG_INSTR_REF !"a", !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !22; example.c:0 line no:50
512B  %12:gr32 = nsw SUB32rr %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !35; example.c:57:16
544B  %12:gr32 = nsw IMUL32rr %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !36; example.c:57:13
560B  $eax = COPY %12:gr32, debug-location !37; example.c:57:5
576B  RET 0, killed $eax, debug-location !37; example.c:57:5

# End machine code for function bar.

AllocationOrder(GR64) = [ $rax $rcx $rdx $rsi $rdi $r8 $r9 $r10 $r11 $rbx $r14 $r15 $r12 $r13 $rbp ]
********** GREEDY REGISTER ALLOCATION **********
********** Function: bar
********** GREEDY REGISTER ALLOCATION **********
********** Function: bar
********** INTERVALS **********
DIL [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
DIH [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
HDI [0B,32r:0)[64r,80r:2)[320r,336r:1) 0@0B-phi 1@320r 2@64r
SIL [0B,16r:0) 0@0B-phi
SIH [0B,16r:0) 0@0B-phi
HSI [0B,16r:0) 0@0B-phi
%2 [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r  weight:INF
%10 [32r,208r:0)[208r,240r:1)[288B,320r:0) 0@32r 1@208r  weight:7.866044e-03
%12 [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r  weight:8.559322e-03
%13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:6.441327e-03
RegMasks: 80r 336r
********** MACHINEINSTRS **********
# Machine code for function bar: NoPHIs, TracksLiveness, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $edi in %4, $esi in %5

0Bbb.0.entry:
  successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%), %bb.2(50.00%)
  liveins: $edi, $esi
16B  %12:gr32 = COPY $esi
32B  %10:gr32 = COPY $edi
48B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
64B  $edi = COPY %10:gr32, debug-location !25; example.c:0
80B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !25; example.c:0
96B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
112B  %13:gr32 = COPY killed $eax, debug-location !25; example.c:0
128B  CMP32rr %10:gr32, %12:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
144B  JCC_1 %bb.2, 14, implicit killed $eflags, debug-location !26; example.c:51:9
160B  JMP_1 %bb.1, debug-location !26; example.c:51:9

176Bbb.1.if.then:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

208B  %10:gr32 = nsw IMUL32rr %10:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
240B  %13:gr32 = nsw ADD32rr %13:gr32(tied-def 0), %10:gr32, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
272B  JMP_1 %bb.3, debug-location !30; example.c:54:5

288Bbb.2.if.else:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)

304B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
320B  $edi = COPY %10:gr32, debug-location !31; example.c:55:20
336B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31; example.c:55:20
352B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
368B  %2:gr32 = COPY killed $eax, debug-location !31; example.c:55:20
400B  %2:gr32 = nsw IMUL32rr %2:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
432B  %2:gr32 = nsw ADD32rr %2:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
448B  %13:gr32 = COPY %2:gr32

464Bbb.3.if.end:
; predecessors: %bb.2, %bb.1

512B  %12:gr32 = nsw SUB32rr %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !35; example.c:57:16
544B  %12:gr32 = nsw IMUL32rr %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !36; example.c:57:13
560B  $eax = COPY %12:gr32, debug-location !37; example.c:57:5
576B  RET 0, killed $eax, debug-location !37; example.c:57:5

# End machine code for function bar.

Enqueuing %2
AllocationOrder(GR32) = [ $eax $ecx $edx $esi $edi $r8d $r9d $r10d $r11d $ebx $ebp $r14d $r15d $r12d $r13d ]
Enqueuing %10
Enqueuing %12
Enqueuing %13

selectOrSplit GR32:%12 [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r  weight:8.559322e-03
hints: $eax $esi
missed hint $eax
Analyze counted 7 instrs in 4 blocks, through 0 blocks.
$eaxstatic = 1.5 worse than no bundles
assigning %12 to $ebx: BH [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r BL [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r HBX [16r,512r:2)[512r,544r:0)[544r,560r:1) 0@512r 1@544r 2@16r

selectOrSplit GR32:%13 [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r  weight:6.441327e-03
hints: $eax
missed hint $eax
Analyze counted 6 instrs in 5 blocks, through 0 blocks.
$eaxstatic = 0.5, v=0, total = 1.0 with bundles EB#1 EB#2.
assigning %13 to $ebp: BPL [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r BPH [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r HBP [112r,240r:3)[240r,288B:1)[288B,400r:3)[448r,464B:0)[464B,544r:2) 0@448r 1@240r 2@464B-phi 3@112r

selectOrSplit GR32:%10 [32r,208r:0)[208r,240r:1)[288B,320r:0) 0@32r 1@208r  weight:7.866044e-03
hints: $edi
missed hint $edi
Analyze counted 6 instrs in 3 blocks, through 0 blocks.
$edistatic = 1.0, v=0, total = 1.0 with bundles EB#1.
Split for $edi in 1 bundles, intv 1.
splitAroundRegion with 2 globals.
%bb.0 [0B;176B), uses 32r-128r, reg-out 1, enter after 80d, defined in block, interference overlaps uses.
    selectIntv 1 -> 1
    enterIntvAfter 80d: valno 0
    useIntv [88r;176B): [88r;176B):1
    enterIntvBefore 32r: not live
    useIntv [32B;88r): [32B;88r):2 [88r;176B):1
%bb.1 [176B;288B), uses 208r-240r, reg-in 1, leave before invalid, killed in block before interference.
    selectIntv 2 -> 1
    useIntv [176B;240r): [32B;88r):2 [88r;240r):1
%bb.2 [288B;464B), uses 320r-320r, reg-in 1, leave before 320r, killed in block before interference.
    selectIntv 1 -> 1
    useIntv [288B;320r): [32B;88r):2 [88r;240r):1 [288B;320r):1
Removing 0 back-copies.
  blit [32r,208r:0): [32r;88r)=2(%16):0 [88r;208r)=1(%15):0
  blit [208r,240r:1): [208r;240r)=1(%15):1
  blit [288B,320r:0): [288B;320r)=1(%15):0
  rewr %bb.032r:2%16:gr32 = COPY $edi
  rewr %bb.1208r:1%15:gr32 = nsw IMUL32rr %10:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
  rewr %bb.1240B:1%13:gr32 = nsw ADD32rr %13:gr32(tied-def 0), %15:gr32, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
  rewr %bb.1208B:1%15:gr32 = nsw IMUL32rr %15:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
  rewr %bb.064B:2$edi = COPY %16:gr32, debug-location !25; example.c:0
  rewr %bb.0128B:1CMP32rr %15:gr32, %12:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
  rewr %bb.2320B:1$edi = COPY %15:gr32, debug-location !31; example.c:55:20
  rewr %bb.088B:2%15:gr32 = COPY %16:gr32
Main interval covers the same 3 blocks as original.
not queueing unused  %14 EMPTY  weight:INF
queuing new interval: %15 [88r,208r:0)[208r,240r:1)[288B,320r:0) 0@88r 1@208r  weight:6.894198e-03
Enqueuing %15
queuing new interval: %16 [32r,88r:0) 0@32r  weight:6.644737e-03
Enqueuing %16

selectOrSplit GR32:%15 [88r,208r:0)[208r,240r:1)[288B,320r:0) 0@88r 1@208r  weight:6.894198e-03
hints: $edi
assigning %15 to $edi: DIL [88r,208r:0)[208r,240r:1)[288B,320r:0) 0@88r 1@208r DIH [88r,208r:0)[208r,240r:1)[288B,320r:0) 0@88r 1@208r HDI [88r,208r:0)[208r,240r:1)[288B,320r:0) 0@88r 1@208r

selectOrSplit GR32:%16 [32r,88r:0) 0@32r  weight:6.644737e-03
hints: $edi
missed hint $edi
Analyze counted 3 instrs in 1 blocks, through 0 blocks.
$edino positive bundles
assigning %16 to $ebp: BPL [32r,88r:0) 0@32r BPH [32r,88r:0) 0@32r HBP [32r,88r:0) 0@32r

selectOrSplit GR32:%2 [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r  weight:INF
hints: $eax $ebp
assigning %2 to $eax: AH [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r AL [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r HAX [368r,400r:2)[400r,432r:0)[432r,448r:1) 0@400r 1@432r 2@368r
Trying to reconcile hints for: %12($ebx)
%12($ebx) is recolorable.
Trying to reconcile hints for: %13($ebp)
%13($ebp) is recolorable.
Trying to reconcile hints for: %16($ebp)
%16($ebp) is recolorable.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: bar
********** REGISTER MAP **********
[%2 -> $eax] GR32
[%12 -> $ebx] GR32
[%13 -> $ebp] GR32
[%15 -> $edi] GR32
[%16 -> $ebp] GR32

0Bbb.0.entry:
  successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%), %bb.2(50.00%)
  liveins: $edi, $esi
16B  %12:gr32 = COPY $esi
32B  %16:gr32 = COPY $edi
48B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
64B  $edi = COPY %16:gr32, debug-location !25; example.c:0
80B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !25; example.c:0
88B  %15:gr32 = COPY killed %16:gr32
96B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
112B  %13:gr32 = COPY $eax, debug-location !25; example.c:0
128B  CMP32rr %15:gr32, %12:gr32, implicit-def $eflags, debug-location !23; example.c:51:9
144B  JCC_1 %bb.2, 14, implicit killed $eflags, debug-location !26; example.c:51:9
160B  JMP_1 %bb.1, debug-location !26; example.c:51:9
> renamable $ebx = COPY $esi
> renamable $ebp = COPY $edi
> ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
> $edi = COPY renamable $ebp, debug-location !25; example.c:0
> CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !25; example.c:0
> renamable $edi = COPY killed renamable $ebp
> ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !25; example.c:0
> renamable $ebp = COPY $eax, debug-location !25; example.c:0
> CMP32rr renamable $edi, renamable $ebx, implicit-def $eflags, debug-location !23; example.c:51:9
> JCC_1 %bb.2, 14, implicit killed $eflags, debug-location !26; example.c:51:9
> JMP_1 %bb.1, debug-location !26; example.c:51:9
176Bbb.1.if.then:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)
  liveins: $ebp, $ebx, $edi
208B  %15:gr32 = nsw IMUL32rr killed %15:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-location !27; example.c:52:23
240B  %13:gr32 = nsw ADD32rr killed %13:gr32(tied-def 0), killed %15:gr32, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
272B  JMP_1 %bb.3, debug-location !30; example.c:54:5
> renamable $edi = nsw IMUL32rr killed renamable $edi(tied-def 0), renamable $ebx, implicit-def dead $eflags, debug-location !27; example.c:52:23
> renamable $ebp = nsw ADD32rr killed renamable $ebp(tied-def 0), killed renamable $edi, implicit-def dead $eflags, debug-instr-number 2, debug-location !29; example.c:52:19
> JMP_1 %bb.3, debug-location !30; example.c:54:5
288Bbb.2.if.else:
; predecessors: %bb.0
  successors: %bb.3(0x80000000); %bb.3(100.00%)
  liveins: $ebp, $ebx, $edi
304B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
320B  $edi = COPY killed %15:gr32, debug-location !31; example.c:55:20
336B  CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31; example.c:55:20
352B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
368B  %2:gr32 = COPY $eax, debug-location !31; example.c:55:20
400B  %2:gr32 = nsw IMUL32rr killed %2:gr32(tied-def 0), killed %13:gr32, implicit-def dead $eflags, debug-location !33; example.c:55:19
432B  %2:gr32 = nsw ADD32rr killed %2:gr32(tied-def 0), %12:gr32, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
448B  %13:gr32 = COPY killed %2:gr32
> ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
> $edi = COPY killed renamable $edi, debug-location !31; example.c:55:20
Identity copy: $edi = COPY killed renamable $edi, debug-location !31; example.c:55:20
  deleted.
> CALL64pcrel32 target-flags(x86-plt) @foo, , implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31; example.c:55:20
> ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !31; example.c:55:20
> renamable $eax = COPY $eax, debug-location !31; example.c:55:20
Identity copy: renamable $eax = COPY $eax, debug-location !31; example.c:55:20
  deleted.
> renamable $eax = nsw IMUL32rr killed renamable $eax(tied-def 0), killed renamable $ebp, implicit-def dead $eflags, debug-location !33; example.c:55:19
> renamable $eax = nsw ADD32rr killed renamable $eax(tied-def 0), renamable $ebx, implicit-def dead $eflags, debug-instr-number 1, debug-location !34; example.c:55:27
> renamable $ebp = COPY killed renamable $eax
464Bbb.3.if.end:
; predecessors: %bb.2, %bb.1
  liveins: $ebp, $ebx
512B  %12:gr32 = nsw SUB32rr killed %12:gr32(tied-def 0), %13:gr32, implicit-def dead $eflags, debug-location !35; example.c:57:16
544B  %12:gr32 = nsw IMUL32rr killed %12:gr32(tied-def 0), killed %13:gr32, implicit-def dead $eflags, debug-location !36; example.c:57:13
560B  $eax = COPY killed %12:gr32, debug-location !37; example.c:57:5
576B  RET 0, $eax, debug-location !37; example.c:57:5
> renamable $ebx = nsw SUB32rr killed renamable $ebx(tied-def 0), renamable $ebp, implicit-def dead $eflags, debug-location !35; example.c:57:16
> renamable $ebx = nsw IMUL32rr killed renamable $ebx(tied-def 0), killed renamable $ebp, implicit-def dead $eflags, debug-location !36; example.c:57:13
> $eax = COPY killed renamable $ebx, debug-location !37; example.c:57:5
> RET 0, $eax, debug-location !37; example.c:57:5
Compiler returned: 0

可以看到Vninfo是以ssa形式进行命名的.

liveness

先看有哪些数据结构

vninfo, SlotIndex
Segment, LiveRange, LiveInterval, LiveRangeUpdater
LiveRangeCalc, LiveIntervalCalc

接下来依次说明.

VNInfo,给define标个号. 每个虚拟变量之间标号是独立的. 比如:

1 2	%1 [224r,240r:0)[240r,256r:1) 0@224r 1@240r weight:0.000000e+00 %2 [416r,432r:0)[432r,448r:1) 0@416r 1@432r weight:0.000000e+00


// llvm/include/llvm/CodeGen/LiveInterval.h
class VNInfo {
  public:
    /// The ID number of this value.
    unsigned id;

    /// The index of the defining instruction.
    SlotIndex def;

    /// Copy from the parameter into this VNInfo.
    void copyFrom(VNInfo &src) {
      def = src.def;
    }

    /// Returns true if this value is defined by a PHI instruction (or was,
    /// PHI instructions may have been eliminated).
    /// PHI-defs begin at a block boundary, all other defs begin at register or
    /// EC slots.
    bool isPHIDef() const { return def.isBlock(); }

};

// llvm/CodeGen/SlotIndexes.h
class SlotIndex {
    enum Slot {
    /// Basic block boundary.  Used for live ranges entering and leaving a
    /// block without being live in the layout neighbor.  Also used as the
    /// def slot of PHI-defs.
    Slot_Block,

    /// Early-clobber register use/def slot.  A live range defined at
    /// Slot_EarlyClobber interferes with normal live ranges killed at
    /// Slot_Register.  Also used as the kill slot for live ranges tied to an
    /// early-clobber def.
    Slot_EarlyClobber,

    /// Normal register use/def slot.  Normal instructions kill and define
    /// register live ranges at this slot.
    Slot_Register,

    /// Dead def kill point.  Kill slot for a live range that is defined by
    /// the same instruction (Slot_Register or Slot_EarlyClobber), but isn't
    /// used anywhere.
    Slot_Dead,

    Slot_Count
    };

    

    PointerIntPair2, unsigned> lie;  // 复用了低2bits放置Slot
}
class IndexListEntry : public ilist_node {
    MachineInstr *mi;
    unsigned index;
}

// slot index管理类， 函数级别
class SlotIndexes{
  using IndexList = simple_ilist;
  IndexList indexList; 
  DenseMap<const MachineInstr *, SlotIndex> mi2iMap;
  SmallVector, 8> MBBRanges;  /// MBBRanges - Map MBB number to (start, stop) indexes.
  SmallVector, 8> idx2MBBMap; // sorted list, 

};

segment表示在一个block块内,某个def-use的生命周期
LiveRange是以ssa形式组织segments的,即一个def对应一个value number, livein/phi也是一个def
LiveInterval是liverange+register
LiveRangeUpdater: 更新segments时候的缓存

// [start, end)
// segment表示
// llvm/include/llvm/CodeGen/LiveInterval.h
struct Segment {
    SlotIndex start;  // Start point of the interval (inclusive)
    SlotIndex end;    // End point of the interval (exclusive)
    VNInfo *valno = nullptr; // identifier for the value contained in this
                            // segment.

    /// Return true if the index is covered by this segment.
    bool contains(SlotIndex I) const {
        return start <= I && I < end;
    }

    /// Return true if the given interval, [S, E), is covered by this segment.
    bool containsInterval(SlotIndex S, SlotIndex E) const {
        assert((S < E) && "Backwards interval?");
        return (start <= S && S < end) && (start < E && E <= end);
    }

    bool operator<(const Segment &Other) const {
    return std::tie(start, end) < std::tie(Other.start, Other.end);
    }
    bool operator==(const Segment &Other) const {
    return start == Other.start && end == Other.end;
    }


    void dump() const;
};

/// This class represents the liveness of a register, stack slot, etc.
/// It manages an ordered list of Segment objects.
/// The Segments are organized in a static single assignment form: At places
/// where a new value is defined or different values reach a CFG join a new
/// segment with a new value number is used.
class LiveRange {
  public:

    using Segments = SmallVector2>;
    using VNInfoList = SmallVector2>;

    Segments segments;   // the liveness segments
    VNInfoList valnos;   // value#'s
}

/// Helper class for performant LiveRange bulk updates.
///
/// Calling LiveRange::addSegment() repeatedly can be expensive on large
/// live ranges because segments after the insertion point may need to be
/// shifted. The LiveRangeUpdater class can defer the shifting when adding
/// many segments in order.
///
/// The LiveRange will be in an invalid state until flush() is called.
class LiveRangeUpdater {
    LiveRange *LR;
    SlotIndex LastStart;
    LiveRange::iterator WriteI;
    LiveRange::iterator ReadI;
    SmallVector16> Spills;
    void mergeSpills();

  public:
    /// Create a LiveRangeUpdater for adding segments to LR.
    /// LR will temporarily be in an invalid state until flush() is called.
    LiveRangeUpdater(LiveRange *lr = nullptr) : LR(lr) {}

    ~LiveRangeUpdater() { flush(); }

    /// Add a segment to LR and coalesce when possible, just like
    /// LR.addSegment(). Segments should be added in increasing start order for
    /// best performance.
    void add(LiveRange::Segment);

    void add(SlotIndex Start, SlotIndex End, VNInfo *VNI) {
      add(LiveRange::Segment(Start, End, VNI));
    }

    /// Return true if the LR is currently in an invalid state, and flush()
    /// needs to be called.
    bool isDirty() const { return LastStart.isValid(); }

    /// Flush the updater state to LR so it is valid and contains all added
    /// segments.
    void flush();

    /// Select a different destination live range.
    void setDest(LiveRange *lr) {
      if (LR != lr && isDirty())
        flush();
      LR = lr;
    }

    /// Get the current destination live range.
    LiveRange *getDest() const { return LR; }

};


class LiveInterval : public LiveRange {
  public:
    using super = LiveRange;

    /// A live range for subregisters. The LaneMask specifies which parts of the
    /// super register are covered by the interval.
    /// (@sa TargetRegisterInfo::getSubRegIndexLaneMask()).
    class SubRange : public LiveRange {
    public:
      SubRange *Next = nullptr;
      LaneBitmask LaneMask; // subreg

      /// Constructs a new SubRange object.
      SubRange(LaneBitmask LaneMask) : LaneMask(LaneMask) {}

      /// Constructs a new SubRange object by copying liveness from @p Other.
      SubRange(LaneBitmask LaneMask, const LiveRange &Other,
               BumpPtrAllocator &Allocator)
        : LiveRange(Other, Allocator), LaneMask(LaneMask) {}

      void print(raw_ostream &OS) const;
      void dump() const;
    };

  private:
    SubRange *SubRanges = nullptr; ///< Single linked list of subregister live
                                   /// ranges.
    const Register Reg; // the register or stack slot of this interval.
    float Weight = 0.0; // weight of this interval
}

LiveRangeCalc, LiveIntervalCalc: 计算和查询接口, 采用增量式更新


// llvm/CodeGen/LiveRangeCalc.cpp
LiveRangeCalc::calculateValues(){
    updateSSA() // 依据domtree来迭代至不动点, (为啥用domtree不太懂)
    updateFromLiveIns() // livein --> LiveRangeUpdater::add
}

博客尽量用text格式

2026-03-18T00:00:00.000Z

感觉图片太多太麻烦了，想尽量在text格式下写。

web图形处理上面有几种解决方案:

用ascii绘制，有点太累了
markdown提供的mermaid和graphviz。mermaid简单但是功能有限，graphviz功能强大。
TikZ，更加专业，https://github.com/kisonecat/tikzjax https://github.com/jhuix-js/tikzjax
base64嵌入，体积会比较大。

关键是文本表示是在框架下已经生成为static/.svg,.png，还是在浏览器里渲染。

win构建llvm

2026-03-15T00:00:00.000Z

构建llvm

以win11+git bash为例

配置

set -x

export COMPILER_DIR=D:/LLVM/bin/ # 替换为一个已有compiler的path
export CC=$COMPILER_DIR/clang.exe
export CXX=$COMPILER_DIR/clang++.exe
export RC_COMPILER=$LLVM_DIR/llvm-rc.exe

mkdir -p build
mkdir -p install

cmake -S ./llvm -B build -G Ninja -DCMAKE_BUILD_TYPE=DEBUG -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_TARGETS_TO_BUILD=X86 -DCMAKE_RC_COMPILER=$RC_COMPILER

构建，ninja
一个线程最少4G内存。4线程16G不一定够用。链接很慢。

2026-3-12记

2026-03-12T00:00:00.000Z

记录下这一年半编译器开发的经验。

编译通过，但是运行结果错误。

如何检查？

先减小问题规模，整出一个最小可复现用例
检查pipeline，parser结果，ir pass结果，isel结果，reg alloc，stack frame等。
verify的重要性，每个不同格式的中间表示转换处需要有verify，保证其流入和流出结果的合法性。
重复上述步骤，直到问题解决。

既然是pipeline模型，那么衔接需要处理好。需重点注意。

编译器挂掉了，没其他信息。一般是各种空指针解引用导致的，linux里面很好处理。
ISA里面还是需要cmp a,b; cset; jmpcc这样的指令。block数量可以少一些，虽然有隐式状态吧。
phi-node-elimination，简单解法很有效。
将合法化和优化分隔开。写在一起很难调试。比如说上面的phi消除，用phi-node-elimination + register-coalescer处理合法性和优化问题。
阶段性测试，必不可少，花费时间写测试很有必要，也是约束项目复杂度的关键措施。想想一命通关的难度。
ir层级表示，4到5层是极限了，每层其实都是一个小解释器。llvm有ast，llvm-ir，mir+MC。算上预处理器就4层了，MC是tablegen送的. 每层都要测试，有自己的结构，层之间的转换。
小即是多，启动目标要尽可能小，而不是摊大饼。多一个环节，复杂度就会上升一级。
关于ai，因为经济问题，只能用免费版本的。效果其实不错。如果还是传统的需求分析，设计，编码，测试流程，ai挺有用的。编码还需要盯着具体实现，最好是划定一个小范围，每步都有git commit。git真是ai code的大爹。

还有编译器后端开发一些经验

phi节点处理
- isel：需要谨慎选择block遍历顺序，RPO是个好选择
- legalize-type：更推荐增量式更新
- phi-elim：也是增量式，冗余copy之后让copy colaescing处理
legalize type需要在legalize opcode之前。因为机器支持的opcode+类型是确定的。
比如在32位机器上运行64位乘法，需要拆成mul-low，mul-high，然后再处理mul32的合法性。
stack frame layout中需要仔细检查下偏移量。多测试下
寄存器分配，看成一个二维图着色问题。一个是变量数目，一个是指令数量（index）

reg0: [10, 14]
reg1: [2, 12]

考虑不同block块的频率不一样，视为频率热力图，greedy算法里面踢出某个块就更容易理解。

图着色坏在不好调试（相对）。

LLVM Inst Schedule

2026-03-10T00:00:00.000Z

LLVM 指令调度

有作用在SelectionDAG和MachineInstr的指令调度。并将调度策略和调度框架分离。

结构

SDep代表一个依赖关系
SUnit代表一个基本单元。
ScheduleDAG，调度DAG的基类。https://llvm.org/doxygen/classllvm_1_1ScheduleDAG.html

ScheduleDAGSDNodes

作用在SelectionDAG上的。
主要在SelectionDAGISel::CodeGenAndEmitDAG()中使用。

MachineScheduler

作用域：MachineBasicBlock。

以AArch64 O2下的pipeline为例。

Pass Arguments: -tti -targetlibinfo -assumption-cache-tracker -targetpassconfig -machinemoduleinfo -profile-summary-info -tbaa -scoped-noalias-aa -collector-metadata -machine-branch-prob -regalloc-evict -regalloc-priority -domtree -basic-aa -aa -objc-arc-contract -pre-isel-intrinsic-lowering -expand-large-div-rem -expand-large-fp-convert -atomic-expand -simplifycfg -domtree -loops -loop-simplify -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -scalar-evolution -loop-data-prefetch -aarch64-falkor-hwpf-fix -basic-aa -loop-simplify -canon-freeze -iv-users -loop-reduce -basic-aa -aa -mergeicmps -loops -lazy-branch-prob -lazy-block-freq -expand-memcmp -gc-lowering -shadow-stack-gc-lowering -lower-constant-intrinsics -unreachableblockelim -loops -postdomtree -branch-prob -block-freq -consthoist -replace-with-veclib -partially-inline-libcalls -expandvp -post-inline-ee-instrument -scalarize-masked-mem-intrin -expand-reductions -loops -tlshoist -aarch64-globals-tagging -stack-safety -domtree -basic-aa -aa -aarch64-stack-tagging -complex-deinterleaving -aa -memoryssa -interleaved-load-combine -domtree -interleaved-access -aarch64-sme-abi -domtree -loops -type-promotion -codegenprepare -domtree -dwarf-eh-prepare -aarch64-promote-const -global-merge -callbrprepare -safe-stack -stack-protector -domtree -basic-aa -aa -loops -postdomtree -branch-prob -debug-ata -lazy-branch-prob -lazy-block-freq -aarch64-isel -machinedomtree -aarch64-local-dynamic-tls-cleanup -finalize-isel -lazy-machine-block-freq -early-tailduplication -opt-phis -slotindexes -stack-coloring -localstackalloc -dead-mi-elimination -machinedomtree -aarch64-condopt -machine-loops -machine-trace-metrics -aarch64-ccmp -lazy-machine-block-freq -machine-combiner -aarch64-cond-br-tuning -machine-trace-metrics -early-ifcvt -aarch64-stp-suppress -aarch64-simdinstr-opt -aarch64-stack-tagging-pre-ra -machinedomtree -machine-loops -machine-block-freq -early-machinelicm -machinedomtree -machine-block-freq -machine-cse -machinepostdomtree -machine-cycles -machine-sink -peephole-opt -dead-mi-elimination -aarch64-mi-peephole-opt -aarch64-dead-defs -detect-dead-lanes -init-undef -processimpdefs -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -machinedomtree -slotindexes -liveintervals -register-coalescer -rename-independent-subregs -machine-scheduler -aarch64-post-coalescer-pass -machine-block-freq -livedebugvars -livestacks -virtregmap -liveregmatrix -edge-bundles -spill-code-placement -lazy-machine-block-freq -machine-opt-remark-emitter -greedy -virtregrewriter -regallocscoringpass -stack-slot-coloring -machine-cp -machinelicm -aarch64-copyelim -aarch64-a57-fp-load-balancing -removeredundantdebugvalues -fixup-statepoint-caller-saved -postra-machine-sink -machinedomtree -machine-loops -machine-block-freq -machinepostdomtree -lazy-machine-block-freq -machine-opt-remark-emitter -shrink-wrap -prologepilog -machine-latecleanup -branch-folder -lazy-machine-block-freq -tailduplication -machine-cp -postrapseudos -aarch64-expand-pseudo -aarch64-ldst-opt -kcfi -aarch64-speculation-hardening -machinedomtree -machine-loops -aarch64-falkor-hwpf-fix-late -postmisched -gc-analysis -machine-block-freq -machinepostdomtree -block-placement -fentry-insert -xray-instrumentation -patchable-function -aarch64-fix-cortex-a53-835769-pass -funclet-layout -stackmap-liveness -livedebugvalues -machine-sanmd -machine-outliner -aarch64-sls-hardening -aarch64-ptrauth -aarch64-branch-targets -branch-relaxation -aarch64-jump-tables -cfi-fixup -lazy-machine-block-freq -machine-opt-remark-emitter -stack-frame-layout -unpack-mi-bundles -lazy-machine-block-freq -machine-opt-remark-emitter
只有一个machine-scheduler，源码在llvm/lib/CodeGen/MachineScheduler.cpp

将Block划分为SchedRegion，每个SchedRegion对应N条MachineInstr，然后在Region中有scheduler进行指令调度。

而AArch64后端中使用createPostMachineScheduler创建了AArch64PostRASchedStrategy作为scheduler。

其继承体系如下：https://llvm.org/doxygen/classllvm_1_1MachineSchedStrategy.html

好复杂的算法和实现。但奇怪的是之前测试CPU2017，各种调度算法影响不大。当然了设置sched.td还是必要的。

寄存器分配简介

2026-02-20T00:00:00.000Z

寄存器分配简介

前置技术 Liveness Analysis， Live Interval, reaching define

Liveness Analysis

经典的数据流分析, 后向(倒序)分析.


live_out[b] = ⋃ (live_in[s] for s ∈ succ(b))
live_in[b]  = use[b] ∪ (live_out[b] − def[b])

live interval

llvm依赖这个，就是 def-use 分段.

reaching define 到达定值

就是某个定义点可以到达什么地方，前向分析。
实现上可以用bitset或者set.

图着色会用到。每次define就生成一个新的ID。


b0:
  v1 = ...
  br b2

b1:
  v1 = ... 
  br b2

b2:
  print(v1)

对其进行def标号后就是


b0:
  v1 = ... ; {d1:v1, } bitset= <10>
  br b2

b1:
  v1 = ... ; {d2:v1, } bitset= <01>
  br b2

b2:
  print(v1)  ; {d1:v1, d2:v1} bitset= <11>

首先, 下面介绍的寄存器分配针对的IR都是非SSA的.
基于SSA来实现的寄存器分配, emm, 没见过.
考虑以下问题: call中abi定义, two address inst, flag的隐式定义.

全局的图着色

参考”高级编译器设计与实现” 16章.


fn alloc_reg(){
    bool success = false;
    do{
        bool coalesce = false;
        do{
            make_web()
            build_adj_matrix()
            coalesce = coalesce_regs()
        }while(!coalesce);

        build_adj_list()
        compute_spill_costs()
        prune_graph()
        success = assign_regs()
        if(success){
            modify_code()
        }else{
            gen_spill_code()
        }

    }while(!success);
}

迭代到不动点.

1. make web

web构造有两种方式

基于 reaching def的结果来构造.
- 先构造duchain
- 基于duchain构造web
直接构造,每个虚拟寄存器就是一个web节点


b0:
2:  v1 = ...
4:  br b2

b1:
6:  v1 = ... 
8:  br b2

b2:
10:  print(v1)
12:  v1 = ...
14:  print(v1)

第一种方式: (参杂了live range信息)
name, defs, uses
web1, {2, 6}, {10}
web2, {12}, {14}

第二种方式:
web1: {2,6,12}, {10, 14}

2. build_adj_matrix

算法核心, 使用下三角邻接矩阵.
关键是如何判定两个web是否干涉.
如果用 Reaching def会有很多假阳性出现. 所以需要liveness来判定.

3. coalesce_regs

会尝试消除一些 a = copy b的指令

4. build_adj_list

基于邻接表就行

5. compute_spill_costs

启发式算法

loop depth
block frequency
num of uses

6. prune_graph

算法的核心. 这一步是将web构成的冲突图排列到一个栈里面, 供assign_regs使用.
有的乐观算法, 选择的节点开始染色. 或者用乐观的启发式算法,删除度>=R的节点推广 .

`7. assign_regs`

给web赋值颜色. 不是真正的修改指令.


success: bool = true
while !stack.empty()
    web = stack.pop()
    c = min_color(web)
    if c > 0
        adjList[web].color = c
    else
        adjList[web].spill = true
        success = false

return success

`8. modify code`

就是很直接的重写

`9. gen_spill_code`

简单来说在def 后生成 store, 在use之前生成load. 注意, 图着色这里是针对所有已经标记为 spill的web进行溢出.

`总结`

不难看出图着色还是比较耗时的. reaching define的计算, adj matrix的计算, 再加上迭代到不动点. 生成的代码质量上, 对live range建模不太完善, spill判定也比较简单.

`linear scan`

从live range出发看待寄存器分配问题. 参考Linear scan register allocation.


reg_alloc(){
  do_instruction_order()
  l =  do_live_intervals_calc()
  l.sort_by_start_point()
  linear_scan(l)

}

linear_scan(live_intervals l){
  active = []
  for live_interval i : l{
    expireOld(i)
    if active.size() == R {
      spillAt(i)
    }else{
      register[i] = free_register.pop()
      active.push(i)
    }
  }
}

expireOld(i){
  for live_interval j in ( active in order of increasing end point ) {
    if j.end >= i.start {
      return 
    }
    remove j from active
    free_register.push(add j.register)
  }
}

spillAt(i){ // 启发式算法
  spill = active.last()
  if spill.end > i.end {
    i.register = spill.register
    spill.location = new stack location

    active.remove(spill)

    active.push(i)
    active.sort_by_end()
  }else{
    i.location = new stack location
  }
}

instruction order 不影响结果正确性,可能影响代码质量
active最大长度是R
spill的依据是启发式算法, 论文里面就是根据live range长度进行判定

改进点:

live intervals太宽泛,可以利用某些空洞
spill计算太简陋, 可以结合更多信息
copy coalescing, 尝试删除a = copy b这样的复制指令

`参考`

高级编译器设计与实现
https://www.cnblogs.com/AANA/p/16315859.html
https://www.cnblogs.com/hsyluxiaoguo/p/18902335
Massimiliano Poletto and Vivek Sarkar. 1999. Linear scan register allocation. ACM Trans. Program. Lang. Syst. 21, 5 (Sept. 1999), 895–913. https://doi.org/10.1145/330249.330250, https://web.cs.ucla.edu/~palsberg/course/cs132/linearscan.pdf



loop 介绍
2025-10-10T00:00:00.000Z
循环，重要性不必多说。
llvm与循环相关的优化有很多：
loop unroll and jam : 循环展开+ 合并
loop unroll
SCEV
loop invariant code motion
loop interchange
loop rotation
loop splitting
loop fusion
loop unswitching
loop vectorization
….
从非结构化的CFG中识别loop：
识别循环迭代变量
Loop 定义
A loop in a control flow graph is a set of nodes S including a header node h, with the following properties:
From any node in S there is a path leading to h 
There is a path from h to any node in S
There is no edge from any node outside S to any node in S other than h
back edge
A control flow graph edge from a node n to a node h that dominates n is called a back edge.
natural loop
The natural loop of a backedge (n,h), where h dominates n, is
 • the set of nodes x such that h dominates x and
 • there is a path from x to n not containing h.
 The header of this loop will be h
 Each back-edge has a corresponding natural loop
nested loop
Suppose:
 – A and B are loops with headers a and b, such that a != b, and b is in A
Then
 – The nodes of B must be a proper subset of the nodes of A
 – We say that loop B is nested within A
 – B is the inner loop
loop识别
假设已经有domtree。
根据loop的定义，从遍历domtree开始构建loop。
用后序方式遍历domtree，即先识别内层loop，然后识别外层loop。
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void initLoopInfo(){
stack = [root];
while(stack.size()){

auto*top = stack.back();

if( !all_children_visited(top) ){
for c in top.children(){
stack.push(c)
}
}else{
stack.pop();

// 1. find back edge
backedgs = []
for pred in top.getBlock().pred(){
if( top.doms( pred ) ){
backedgs.push(pred)
}
}
if (pred.size()){
loop = createLoop()
discoverLoop(loop, backedgs)
}
}
}
}

// 有回边，loop header可以查找循环体了。
// 寻找backedges的前驱即可。
void discoverLoop(loop, backedgs){

while(backedgs.size()){
auto* n = backedgs.back();
backedgs.pop_back();

sub_loop = info.get(n)
if(sub_loop == nullptr){
if(!loop.getHeader().dom(n)){
continue
}
loop.add(n)
for p in n.pred(){
backedgs.push(p)
}
}else{
// 有内层循环了
sub = sub_loop->getOuterMostLoop()
loop.add_sub(sub)

n = sub.getHeader()
// 不处理sub对应的所有block
for p in n.preds(){
if( getLoop(p) != sub ){
backedgs.push(p)
}
}
}

}
}

Compilers I Chapter 1: Introduction
On loops, dominators, and dominance frontiers (acm.org)
Microsoft PowerPoint - loopOptimization [Compatibility Mode] (utexas.edu)


SSA构建和销毁
2025-09-20T00:00:00.000Z
phinode的创建和消除
1. SSA构建算法
依赖：
dom tree
DF
llvm ir基础知识
对以下c代码
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int foo(int a){
int b = a;
return b;
}
clang会生成类似这种IR
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define i32 @foo(i32 %a){
%pa = alloc i32
%pb = alloc i32
store %a, %pa
store %a, %pb
%b1 = load %pb
ret i32 %b1
}
我们能看到llvm采用了alloc+load+store指令来实现c中局部变量的存放。
这里参数处理i32 %a; store %a, %pa实际上是个比较复杂的话题，按下不表。
这段IR的有很多冗余的load/store, 有没有什么办法消除掉呢？
SROA（mem2reg）！
预期的IR
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define i32 @foo(i32 %a){
ret i32 %a
}
如果控制流比较复杂呢？
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int b = a;
if(a > 10){
b = b + a;
}else{
b = b * a;
}
return b;
=> 
ir
bb0:
  %pb = alloc i32
  store %a, %pb
  %c = CMP_GT %a, 10
  br %c, %bb1, %bb2

bb1:
  %b0 = load %pb
  %b1 = add %b0, %a
  store %b1, %pb
  br %bb4

bb3:
  %b2 = load %pb
  %b3 = mul %b2, %a
  store %b3, %pb
  br %bb4
bb4:
  %b4 = load %pb
  ret %b4
这里我们发现，如果想要正确删除掉这些load/store，我们需要引入phinode,而且必须拿到控制流信息。phinode是个逻辑节点，在实际的CPU上没对应的指令/寄存器表示。所以我们在生成实际的汇编前需要再删除掉phi。
接下来看如何实现SSA构建：
原理分为两步, insertPHI, Rename， 伪代码如下：
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procedure InsertPHI(variable_list)

    for each variable v in variable_list
        WorkList ← ∅
        EverOnWorkList ← ∅
        AlreadyHasPhiFunc ← ∅
        for each node n containing an assignment to v
            WorkList ← WorkList ∪ {n}
        end

        EverOnWorkList ← WorkList
        while WorkList ≠ ∅
            Remove some node n from WorkList
            for each d ∈ DF(n)
                if d ∉ AlreadyHasPhiFunc
                    Insert a φ-function for v at d
                    AlreadyHasPhiFunc ← AlreadyHasPhiFunc ∪ {d}
                    if d ∉ EverOnWorkList
                        WorkList ← WorkList ∪ {d}
                        EverOnWorkList ← EverOnWorkList ∪ {d}
                    end
                end
            end
        end
    end
end procedure

  

procedure GenName(variable v)
    vn = new Value(v)
    Push vn onto Stacks[v]
    return v
end procedure

  

procedure Rename(block b)

    if b previously visited return
    for each φ-function p in b
        v = LHS(p)
        vn = GenName(v) and replace v with vn
    end

    for each statement s in b (in order)
        for each variable v ∈ RHS(s)
            replace v by Top(Stacks[v])
        end

        for each variable v ∈ LHS(s)
            vn = GenName(v) and replace v with vn
        end

        for each s ∈ succ(b) (in CFG)
            j ← position in s’s φ-function corresponding to block b
            for each φ-function p in s
                replace the jth operand of RHS(p) by Top(Stacks[v])
            end
        end
    end

    for each s ∈ child(b) (in DT)
        Rename(s)
    end

    for each φ-function or statement t in b
        for each vi ∈ LHS(t)
            Pop(Stacks[v])
        end
    end
end procedure

SSAConstruction:
    InsertPHI(list)
    Rename(entry)
end
我们看到这种伪代码的形式和LLVMIR区别很大。因为IR格式不一样，接下来看llvm ir下如何实现mem2reg
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mem2reg(Function f){
list = []
for inst in f.entry(){
if inst is alloc and isPromotable(inst){
// 有些alloc不能被删除，like volatile
list.push(inst)
}
}
if list.empty() return

Phi2Alloc = InsertPHI(list)

// init map: alloc -> stack
// with first value undef
incomings_map = {} 
for alloc in list {
incomings_map[alloc] = [undef]
}

Rename(f.entry(), incomings_map, Phi2Alloc)
}

InsertPHI(list){
Phi2Alloc = {}
for alloc in list{
WorkList = []
for user in alloc.use_list(){
if user is store {
WorkList.push(user.parent())
}
}
EverOnWorkList = WorkList.clone()
AlreadyHasPhi = []

while !WorkList.empty() {
n = WorkList.pop()

for d in DF(n) {
if d not in AlreadyHasPhi {
phi = create_phi()
phi.set_all_incomings(undef)
d.insert_front(phi)
Phi2Alloc[phi] = alloc

AlreadyHasPhi.add(d)
if d not in EverOnWorkList {
WorkList.push(d)
EverOnWorkList.push(d)
}
}
}
}
}
return Phi2Alloc
}

PhiRename(bb, incomings_map, Phi2Alloc){
if bb visited, return
for inst in bb {
if inst is phi {
if inst not in Phi2Alloc
continue
alloc = Phi2Alloc[inst]
incomings_map[alloc].push(phi) // update top

continue
}
if inst is load {
// %inst = load %address
ad = inst.get_address();
if(ad is alloc) {
top = incomings_map[ad].top();
inst.replaceAllUsesWith(top)
}
continue;
}
if inst is store {
ad = inst.get_address()
// store %x, %address
if ad is alloc {
// update top
incomings_map[ad].push(inst.getValue());
}
}
}
for succ in b.getSuccessors() { // cfg
for phi in succ.getPhiNodes() {
alloc = Phi2Alloc[phi]
top = incomings_map[alloc].top()
phi.update_by_block(b, top) // update for incoming
}
}

for child in DomTree(b).children() {
// may cause stack over flow...
Rename(child, incomings_map, Phi2Alloc)
}

// do pop stack
for inst in b {
if inst is phi {
alloc = Phi2Alloc[phi]
incomings_map[alloc].pop()
continue
}

if inst is store {
ad = inst.getAddress()
incomings_map[ad].pop()
}
}
}

当然，以上代码不是llvm mem2reg实际实现代码。
llvm实现做了一些优化，domtree遍历优化，特殊情况处理等。
2. SSA destruction
如何销毁SSA形式，删除phinode。
llvm的phi-elimination是在mir阶段发生。
一般来说，SSA destruction是将phinode替换为copy指令。
暴力做法，对于p = phi (%a1, %bb1), (%a2, %bb2) ....，在bb1,bb2… 尾部插入 p = copy %a... 然后删除掉phi节点。但是该做法结果不对。
考虑到lost copy problem和swap problem：
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// Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency
// https://inria.hal.science/inria-00349925v1/document

lost copy problem:

b0:
x1 =...
jmp b1

b1:  
x2 = phi(x1, x3)      
x3 = x2 + 1  
...
jmp p, b1, b2


-----------------------

swap problem:

b0:
a1 =...
b1 =...
jmp b1

b1:          
a2 = phi(a1, b2)      
b2 = phi(b1, a2)      
    ...                      
jmp p, b1, b2          

我们的暴力算法会生成
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swap problem:
b0:
a1 = ...
b1 = ...
a2 = copy a1
b2 = copy b1
jump b1
b1:
a2 = copy b2 <--- 没有swap
b2 = copy a2

if p jump b1
jump b2
b2:
...


--------------------------------------------

lost-copy-problem

b0:
x1 = ...
x2 = copy x1
jump b1
b1:
x3 = x2 + 1
x2 = copy x3
if p jump b1
jump b2
b2:
... = x2  <---- 这里错误

split critical edges
图中红边就是critical edge: 
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digraph G {
    // 不可见节点（不显示标签）
    xxx [label="", shape=none, width=0, height=0];
    others [label="", shape=none, width=0, height=0];
    
    // 可见节点
    b1 [label="b1", shape=circle, style=filled, fillcolor=lightgray];
    b2 [label="b2", shape=circle, style=filled, fillcolor=lightgray];
    
    // 边
    xxx -> b2 [];  
    b1 -> b2 [color=red, penwidth=2];
    b1 -> others [];  
    
    // 调整布局
    rankdir=TD;  // 从左到右排列
}

对lost copy和swap应用该算法：
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lost-copy-problem

b0:
x1 =...
x2 = copy x1
jmp b1

b1:
x3 = x2 + 1
jmp p, b3, b2

b3:
x2 = copy x3
jmp b1

b2:
... = x2

---------------------------------------------------

swap problem

bb0:
a1 =...
b1 =...
a2 = copy a1
b2 = copy b1
jmp bb1

bb1:

jmp p, bb3, bb2

bb3:
a2 = copy b2  <--- 没有swap
b2 = copy a2
jmp bb1

bb2:
... = a2
... = b2

swap problem结果看起来不太对哦。
看起来是插入copy出了问题, 再看一眼a2=phi(a1, b2);b2=phi(b1,a2) a2, b2形成了环。
是个环。。。
我们发现swap problem中
a2和b2的生命周期重叠了
并且插入copy方式也需要改进
isolating phi + parallel copy
先介绍几个概念
CSSA(Conventional SSA) form is defined as SSA form for which each phi-web is interference-free.
TSSA(Transformed SSA) form is non-conventional SSA, may have phi-web is not interference-free.
swap problem和lost-copy problem中 都是TSSA，而不是CSSA。
如何将TSSA转换为CSSA？并且在CSSA中插入copy是否还需要注意类似swapproblem的情况？
所以我们接下来的算法步骤是：
Insert parallel copies for all φ-functions （TSSA => CSSA）
eliminate phis in CSSA
Sequentialize parallel copies, possibly with one more variable and some additional copies
some optimization
首先转换为cssa格式
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lost copy problem

b0:
x1 =...
x1' = copy x1
jmp b1

b1:
x2' = phi(x1', x3')
x2 = copy x2'
x3 = x2 + 1
x3' = copy x3

jmp p, b1, b2

b2:
... = x2


----------------------------------------

swap problem:

B0:
a1 =...
b1 =...
a1' = copy a1
b1' = copy b1
jmp B1

B1:
a2' = phi(a1', b2')
b2' = phi(b1', a2')
a2 = copy a2'
b2 = copy b2'
b2' = copy b2
a2' = copy a2
   ...
jmp p, B1, B2

B2:
... = a2
... = b2

消除phi节点后：
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lost copy problem

b0:
x1 =...
x1' = copy x1
x2' = copy x1'      // x1' in x2' = phi(x1', x3')
jmp b1

b1:
x2 = copy x2'
x3 = x2 + 1
x3' = copy x3
x2' = x3'            // x3' in x2' = phi(x1', x3')
jmp p, b1, b2

b2:
... = x2


----------------------------------------

swap problem:

B0:
a1 =...
b1 =...
a1' = copy a1
b1' = copy b1
a2' = copy a1'   // a1' in a2' = phi(a1', b2')
b2' = copy b1' // b1' in b2' = phi(b1', a2')
jmp B1

B1:
a2 = copy a2'
b2 = copy b2'
b2' = copy b2
a2' = copy a2
   a2' = copy b2'  // a2' in a2' = phi(a1', b2')
b2' = copy a2'  // b2' in b2' = phi(b1', a2')
jmp p, B1, B2

B2:
... = a2
... = b2

上一小节提到的swap中copy的问题仍然存在，所以接下来要介绍，parallel copies的概念。
我们将这些插入的copy指令视为parallel copies，然后采用算法求解copy插入顺序
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// Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency (https://inria.hal.science/inria-00349925v1/document)

// @args
// Set P of parallel copies of the form a -> b, a != b
// n: one extra fresh variable
// @output:  List of copies in sequential order
def parallel_copy_sequentialization(P:set, n: variable) 

ready = []
to_do = []
pred(n) = none // a map

for a -> b in p
loc(b) = none               // init
pred(b) = none
end for

for a -> b in p    
loc(a) = a                    /* needed and not copied yet */
pred(b) = a                   /* (unique) predecessor *
to_do.append(b)               /* copy into b to be done */

for a->b in p
if loc(b) == none
ready.append(b)            /* b is not used and can be overwritten */

while to_do != []
while ready != []
b = ready.pop()
a = pred(b)
c = loc(a)
emit copy c -> b

loc(a) = b
if a == c and pred(a) != none
ready.append(a)
b = to_do.pop()
l = loc(pred(b))
if b == l
emit copy b -> n
loc(b) = n
ready.append(b)

不幸的是，这个算法有点小问题。
实际上是个图遍历算法：cc09.pdf
我们用python写个demo：
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class Copy:
    def __init__(self, src, dst):
        self.src = src
        self.dst = dst
    def __repr__(self):
        return "%s <- %s" % (self.dst, self.src)

def seq_copy(seq):
    ready = []
    todo = []
    pred = {}
    loc = {}
    n = "tmp"
  
    pred[n] = None
    for i in seq:
        a = i.src
        b = i.dst
        loc[b] = None
        pred[a] = None

    for i in seq:
        a = i.src
        b = i.dst
        loc[a] = a
        pred[b] = a
        todo.append(b)

    for i in seq:
        a = i.src
        b = i.dst
        if loc[b] is None:
            ready.append(b)


    while len(todo) != 0:
        while len(ready) != 0:
            b = ready.pop()
            a = pred[b]
            c = loc[a]
            print("emit copy {} <- {}".format(b, c))
            loc[a] = b
            if a ==c and pred[a] is not None:
                ready.append(a)
        b = todo.pop(0)
        l = loc[pred[b]]

        if b == l: # <<<<< 这里
            print("emit copy {}<- {}".format(n, b))
            loc[b] = n
            ready.append(b)
           
seq= [
    Copy("b", "a"),
    Copy("a", "b"),
]

seq_copy(seq)
运行脚本，啥也不输出。
但是如果我们将 b==l改成b!=l, 就会输出
emit copy tmp<- a
emit copy a <- b
emit copy b <- tmp
至此，我们完成了phi-elimination的一半，合法化问题解决了。但是性能问题没解决。
对于lost copy problem，在BB块前插入copy指令是必须的。（如果采用Split Critical Edges的方式，循环的代码质量会下降）
对于swap problem，需检测环的出现。
copy插入位置问题，lost copy 和swap problem插入顺序还不一样。
这帮人写论文能不能靠谱点
llvm采用的算法
llvm有split critical edge也有不依赖split critical edge的实现。
parallel copy面对如下代码还是有些问题
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// 格式化整型的代码实现
int value = ....;
do{
int a = value % base;
value = value / base;

buf[len++] = a;

} while(value)

原因还是copy插入顺序。（parallel copies的遍历顺序）
解决方法，额。
根据llvm中split critical edges的方法。
如果phi的incoming block是critical edge 的src block，例如 bb0：a0 = phi a1,bb1, a2, bb2 其中bb2是critical edge，那么在bb1尾部创建tmp = copy a1, 在bb0头部a0 = copy tmp, 在bb2尾部tmp = copy a2.
如果没有critical edge, 直接copy，bb1尾部创建a0 = copy a1,bb2尾部a0 = copy a2.
很简单的实现，但是还是挺有效。。。
https://gcc.godbolt.org/z/aMWPjK3a9
为什么不split block呢？因为跳转太多会导致性能下降，特别是在loop中。
优化问题
关键字：copy de-coalescing
即如何最小化插入copy指令 
在CSSA上面对parallel copies 优化
先生成很多冗余的copy指令，然后再优化这些copy指令
第一种方式有些困难，个人认为难点在于parallel copies相关生命周期如何计算。
第二种方式就很传统了, interference graph + union find， 不干涉的放在一个点集里面。
others
我们重新关注下parallel copies 。
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对于


bb1:
a1 = ...
b1 = ...
c1 = ...
jump bb

bb2:
a2 = ...
b2 = ...
c2 = ...
jump bb

bb3:
a3 = ...
b3 = ...
c3 = ...
jump bb

bb:
a = phi(a1, a2, a3)
b = phi(b1, b2, b3)
c = phi(c1, c2, c3)

注意\\可能会被识别为\, 用\newline更好
$\begin{bmatrix} a \newline b \newline c \end{bmatrix}
 = Φ \begin{bmatrix} a1 & a2 & a3 \newline b1 & b2 & b3 \newline c1 &c2 & c3 \end{bmatrix} $
那么对于bb1来说，就有parallel copies: $a \gets a1, b \gets b1, c \gets c1$。
其对应的Location Transfer Graph为$G = (V, E), V = \lbrace a,b,c, a1, b1, c1\rbrace, E = \lbrace a \gets a1, b \gets b1, c \gets c1 \rbrace$
再看下swap problem里面的
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a2 = phi(a1, b2)
b2 = phi(b1, a2)
前驱1的parallel copies
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flowchart TD
  a1 --> a2
  b1 --> b2
前驱2的parallel copies
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flowchart TD
  a2 --> b2
  b2 --> a2
参考
https://www.cs.utexas.edu/~pingali/CS380C/2010/papers/ssaCytron.pdf
https://ics.uci.edu/~yeouln/course/ssa.pdf
Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency
cc09.pdf
llvm实现。
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int cond_random();

void swap_p(int a, int b, int *arr){

    while(cond_random() ){
        int tmp = a;
        a = b;
        b = tmp;
    }
    *arr++ = a;
    *arr++ = b;
}


void lost_copy(int a, int *p){

    while(cond_random()){
        a+=1;
    }
    *p = a;
}

lost copy
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# Machine code for function lost_copy(int, int*): IsSSA, TracksLiveness
Function Live Ins: $edi in %3, $rsi in %4

bb.0.entry:
  successors: %bb.1(0x80000000); %bb.1(100.00%)
  liveins: $edi, $rsi
  %4:gr64 = COPY killed $rsi
  %3:gr32 = COPY killed $edi
  %0:gr32 = DEC32r killed %3:gr32(tied-def 0), implicit-def dead $eflags; example.cpp:19:5

bb.1.while.cond:
; predecessors: %bb.0, %bb.1
  successors: %bb.2(0x04000000), %bb.1(0x7c000000); %bb.2(3.12%), %bb.1(96.88%)

  %1:gr32 = PHI %0:gr32, %bb.0, %2:gr32, %bb.1, debug-instr-number 1
  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:19:11
  CALL64pcrel32 target-flags(x86-plt) @cond_random(), , implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax; example.cpp:19:11
  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:19:11
  %5:gr32 = COPY killed $eax; example.cpp:19:11
  %2:gr32 = INC32r killed %1:gr32(tied-def 0), implicit-def dead $eflags; example.cpp:19:5
  TEST32rr killed %5:gr32, %5:gr32, implicit-def $eflags; example.cpp:19:11
  JCC_1 %bb.1, 5, implicit killed $eflags; example.cpp:19:5
  JMP_1 %bb.2; example.cpp:19:5

bb.2.while.end:
; predecessors: %bb.1

  MOV32mr killed %4:gr64, 1, $noreg, 0, $noreg, killed %2:gr32 :: (store (s32) into %ir.p); example.cpp:22:8
  RET 0; example.cpp:23:1

# End machine code for function lost_copy(int, int*).


# Machine code for function lost_copy(int, int*): NoPHIs, TracksLiveness
Function Live Ins: $edi in %3, $rsi in %4

bb.0.entry:
  successors: %bb.1(0x80000000); %bb.1(100.00%)
  liveins: $edi, $rsi
  %4:gr64 = COPY killed $rsi
  %3:gr32 = COPY killed $edi
  %0:gr32 = DEC32r killed %3:gr32(tied-def 0), implicit-def dead $eflags; example.cpp:19:5
  %6:gr32 = COPY killed %0:gr32

bb.1.while.cond:
; predecessors: %bb.0, %bb.1
  successors: %bb.2(0x04000000), %bb.1(0x7c000000); %bb.2(3.12%), %bb.1(96.88%)

  %1:gr32 = COPY killed %6:gr32
  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:19:11
  CALL64pcrel32 target-flags(x86-plt) @cond_random(), , implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax; example.cpp:19:11
  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:19:11
  %5:gr32 = COPY killed $eax; example.cpp:19:11
  %2:gr32 = INC32r killed %1:gr32(tied-def 0), implicit-def dead $eflags; example.cpp:19:5
  TEST32rr killed %5:gr32, %5:gr32, implicit-def $eflags; example.cpp:19:11
  %6:gr32 = COPY %2:gr32
  JCC_1 %bb.1, 5, implicit killed $eflags; example.cpp:19:5
  JMP_1 %bb.2; example.cpp:19:5

bb.2.while.end:
; predecessors: %bb.1

  MOV32mr killed %4:gr64, 1, $noreg, 0, $noreg, killed %2:gr32 :: (store (s32) into %ir.p); example.cpp:22:8
  RET 0; example.cpp:23:1

# End machine code for function lost_copy(int, int*).

# Machine code for function lost_copy(int, int*): NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $edi in %3, $rsi in %4

0Bbb.0.entry:
  successors: %bb.1(0x80000000); %bb.1(100.00%)
  liveins: $edi, $rsi
16B  %4:gr64 = COPY $rsi
32B  %6:gr32 = COPY $edi
64B  %6:gr32 = DEC32r %6:gr32(tied-def 0), implicit-def dead $eflags; example.cpp:19:5

96Bbb.1.while.cond:
; predecessors: %bb.0, %bb.1
  successors: %bb.2(0x04000000), %bb.1(0x7c000000); %bb.2(3.12%), %bb.1(96.88%)

128B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:19:11
144B  CALL64pcrel32 target-flags(x86-plt) @cond_random(), , implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax; example.cpp:19:11
160B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:19:11
176B  %5:gr32 = COPY killed $eax; example.cpp:19:11
208B  %6:gr32 = INC32r %6:gr32(tied-def 0), implicit-def dead $eflags; example.cpp:19:5
224B  TEST32rr %5:gr32, %5:gr32, implicit-def $eflags; example.cpp:19:11
256B  JCC_1 %bb.1, 5, implicit killed $eflags; example.cpp:19:5
272B  JMP_1 %bb.2; example.cpp:19:5

288Bbb.2.while.end:
; predecessors: %bb.1

304B  MOV32mr %4:gr64, 1, $noreg, 0, $noreg, %6:gr32 :: (store (s32) into %ir.p); example.cpp:22:8
320B  RET 0; example.cpp:23:1

# End machine code for function lost_copy(int, int*).

swap
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# Machine code for function swap_p(int, int, int*): IsSSA, TracksLiveness
Function Live Ins: $edi in %2, $esi in %3, $rdx in %4

bb.0.entry:
  successors: %bb.1(0x80000000); %bb.1(100.00%)
  liveins: $edi, $esi, $rdx
  %4:gr64 = COPY killed $rdx
  %3:gr32 = COPY killed $esi
  %2:gr32 = COPY killed $edi

bb.1.while.cond:
; predecessors: %bb.0, %bb.1
  successors: %bb.2(0x04000000), %bb.1(0x7c000000); %bb.2(3.12%), %bb.1(96.88%)

  %0:gr32 = PHI %3:gr32, %bb.0, %1:gr32, %bb.1, debug-instr-number 2
  %1:gr32 = PHI %2:gr32, %bb.0, %0:gr32, %bb.1, debug-instr-number 1
  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:7:11
  CALL64pcrel32 target-flags(x86-plt) @cond_random(), , implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax; example.cpp:7:11
  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:7:11
  %5:gr32 = COPY killed $eax; example.cpp:7:11
  TEST32rr killed %5:gr32, %5:gr32, implicit-def $eflags; example.cpp:7:11
  JCC_1 %bb.1, 5, implicit killed $eflags; example.cpp:7:5
  JMP_1 %bb.2; example.cpp:7:5

bb.2.while.end:
; predecessors: %bb.1

  MOV32mr %4:gr64, 1, $noreg, 0, $noreg, killed %1:gr32 :: (store (s32) into %ir.arr); example.cpp:12:12
  MOV32mr killed %4:gr64, 1, $noreg, 4, $noreg, killed %0:gr32 :: (store (s32) into %ir.incdec.ptr); example.cpp:13:12
  RET 0; example.cpp:14:1

# End machine code for function swap_p(int, int, int*).


# Machine code for function swap_p(int, int, int*): NoPHIs, TracksLiveness
Function Live Ins: $edi in %2, $esi in %3, $rdx in %4

bb.0.entry:
  successors: %bb.1(0x80000000); %bb.1(100.00%)
  liveins: $edi, $esi, $rdx
  %4:gr64 = COPY killed $rdx
  %3:gr32 = COPY killed $esi
  %2:gr32 = COPY killed $edi
  %6:gr32 = COPY killed %3:gr32
  %7:gr32 = COPY killed %2:gr32

bb.1.while.cond:
; predecessors: %bb.0, %bb.1
  successors: %bb.2(0x04000000), %bb.1(0x7c000000); %bb.2(3.12%), %bb.1(96.88%)

  %1:gr32 = COPY killed %7:gr32
  %0:gr32 = COPY killed %6:gr32
  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:7:11
  CALL64pcrel32 target-flags(x86-plt) @cond_random(), , implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax; example.cpp:7:11
  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:7:11
  %5:gr32 = COPY killed $eax; example.cpp:7:11
  TEST32rr killed %5:gr32, %5:gr32, implicit-def $eflags; example.cpp:7:11
  %6:gr32 = COPY %1:gr32
  %7:gr32 = COPY %0:gr32
  JCC_1 %bb.1, 5, implicit killed $eflags; example.cpp:7:5
  JMP_1 %bb.2; example.cpp:7:5

bb.2.while.end:
; predecessors: %bb.1

  MOV32mr %4:gr64, 1, $noreg, 0, $noreg, killed %1:gr32 :: (store (s32) into %ir.arr); example.cpp:12:12
  MOV32mr killed %4:gr64, 1, $noreg, 4, $noreg, killed %0:gr32 :: (store (s32) into %ir.incdec.ptr); example.cpp:13:12
  RET 0; example.cpp:14:1

# End machine code for function swap_p(int, int, int*).


# Machine code for function swap_p(int, int, int*): NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $edi in %2, $esi in %3, $rdx in %4

0Bbb.0.entry:
  successors: %bb.1(0x80000000); %bb.1(100.00%)
  liveins: $edi, $esi, $rdx
16B  %4:gr64 = COPY $rdx
32B  %6:gr32 = COPY $esi
48B  %7:gr32 = COPY $edi

96Bbb.1.while.cond:
; predecessors: %bb.0, %bb.1
  successors: %bb.2(0x04000000), %bb.1(0x7c000000); %bb.2(3.12%), %bb.1(96.88%)

112B  %1:gr32 = COPY %7:gr32
128B  %7:gr32 = COPY %6:gr32
144B  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:7:11
160B  CALL64pcrel32 target-flags(x86-plt) @cond_random(), , implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax; example.cpp:7:11
176B  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp; example.cpp:7:11
192B  %5:gr32 = COPY killed $eax; example.cpp:7:11
208B  TEST32rr %5:gr32, %5:gr32, implicit-def $eflags; example.cpp:7:11
224B  %6:gr32 = COPY %1:gr32
256B  JCC_1 %bb.1, 5, implicit killed $eflags; example.cpp:7:5
272B  JMP_1 %bb.2; example.cpp:7:5

288Bbb.2.while.end:
; predecessors: %bb.1

304B  MOV32mr %4:gr64, 1, $noreg, 0, $noreg, %1:gr32 :: (store (s32) into %ir.arr); example.cpp:12:12
320B  MOV32mr %4:gr64, 1, $noreg, 4, $noreg, %7:gr32 :: (store (s32) into %ir.incdec.ptr); example.cpp:13:12
336B  RET 0; example.cpp:14:1

# End machine code for function swap_p(int, int, int*).